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6-1 key features preliminary programmable peripheral psd5xx family field-programmable microcontroller peripherals o complete family of field programmable microcontroller peripherals enables the user to efficiently implement a highly integrated embedded control system in a short time. the psd5xx family has a variety of functions such as zplds , i/o ports, counter/timers, interrupt controller, power management, eprom and sram. o ?o glue-logic?user programmable interface to 8 or 16 bit microcontroller multiplexed and non-multiplexed bus. the bus control logic can directly decode control signals generated by 8031, 80196, 80186, 68hc11, 68hc16, 683xx, 16000, z80, and z8 architecture. extended address capability up to 24 bits of address. o a range of zpld (zero power pld) architectures have up to 30 macrocells, 61 inputs and 140 output product terms. includes 3 functional zplds which enable the user to efficiently implement a variety of state machines, logic functions, address decoding and control of the internal psd5xx functional blocks . o the zplds use a zero power cmos technology that reduces the device standby current to 10 a typical. unused product terms are disabled to reduce operating power. o up to 40 i/o ports that can be individually configured by the user as standard mcu i/o ports, pld i/o, latched address outputs and special function i/o. two eight bit i/o ports can be configured as open drain outputs. o four 16 bit counter/timers, that have 5 modes of operation and can be controlled by the peripheral pld (ppld) macrocells. modes of operation are pulse, waveform, time capture, event counting and watch dog timer (or real time clock). the counter/timer clock input has a prescaler that can scale the input frequency from 4 to 280. o eight input priority encoded interrupt controller. four interrupts are generated by the ppld and are user defined. the other four interrupts are generated by the counter/timers terminal count flags. each interrupt input can be individually masked and configured as edge or level sensitive. o the psd5xx family contains eprom densities of 256 kbit, 512 kbit and 1 mbit that can be configured as 8 or 16 bit data width. the eprom is divided into 4 equal blocks that can be mapped to different address spaces. access time is 70 ns which includes address latching and decoder pld (dpld) decoding. the eprom has a low power mode that is controlled by the cmiser-bit. o the psd5xx family contains a 16kbit standby sram that can be configured as 8 or 16 bit data width. access time is 70 ns which includes address latching and decoder pld (dpld) decoding. the sram can be used as standby storage if standby power is supplied to the vstby pin. switching between v cc and vstby occurs automatically. o page logic is connected to the zplds and enables address space expansion of microcontrollers with limited address space capability. up to 16 pages are available.
psd5xx family 6-2 key features (cont.) o a security bit prevents reading the psd5xx configuration, zpld and eprom contents. this inhibits copying the device on a programmer. o port a can be used as a buffered microcontroller data bus (peripheral i/o mode) of the microcontroller bus. this provides easy access to sub-systems that require more drive on the data bus or accessing a resource that is shared by another mcu or dma controller. o low power operation is achieved by using a power management unit (pmu) that enables automatic standby modes in the eprom, sram, and zplds. it also disables the clock to the zpld and counter/timer. also available is an automatic power down mode using the ale signal. a sleep mode is available that consumes only 10 a standby power consumption. o psd5xx standard versions are ideal for general purpose applications. o psd5xxm mask-programmable versions are ideal for code-stable, high-volume low cost applications. o package choices include 68 pin plastic (j) and ceramic (l) chip carriers. o the psd5xx family is supported with pc based psdsoft ms-windows compatible development tools. offering abel as a design entry method, (psdabel ), an efficient fitter, address translator, magicpro programmer and a full chip simulator (psdsilos iii ) are included. the psd5xx series of field programmable microcontroller peripherals represent a major advance in the evolution of programmable peripherals. they combine an innovative architecture with state of the art technology to provide user programmability (logic, functions, memory), flexibility, high integration, optimum performance, low power . for example, the psd513b1 can implement a full peripheral subsystem and has the following features: o three zplds with a total of 61 inputs, 140 product terms outputs, 30 macrocells and 24 i/o pins. o 40 individually programmable i/o pins that are divided into 5 ports. o four 16-bit peripheral pld (ppld)-controlled counter/timers that can perform pulse, waveform, time capture, event counting and watch dog functions. o eight input priority encoded interrupt controller. four interrupts are generated by the counter/timer unit and the other four can be user defined through the ppld. o 4-bit page register o 1 mbit reprogrammable eprom consists of four 256 kbit blocks. o 16 kbit of standby sram that can automatically switch into standby mode. o power management unit with automatic standby and sleep modes. o security mode. figure 1 is a top level block diagram of the psd5xx. refer to table 1 and other sections for details on functionality, dc/ac specification, packages and ordering information. general description
psd5xx family 6-3 prog. bus intrf adio port control rd, wr ad0 ?ad15 pc0 ?pc7 pd0 ?pd7 clkin watch dog output interrupt output clkin 60 clkin terminal counts page reg. zpld input bus global config. & security prog. port port a prog. port port b power manager unit vstdby pa0 ?pa7 pb0 ?pb7 prog. port port e prog. port port d prog. port port c pe0 ?pe7 address/data/control bus 4 macrocells 2 macrocells 8pt 4pt 2pt port a macrocells port b macrocells port e macrocells 27pt 61 60 80pt 11pt clkin four 16 - bit 256k 1m bit eprom 16 k bits sram i/o decoder eprom select sram select peripheral selects macrocell feedback or port input csiop general pld (gpld) peripheral pld (ppld) interrupt controller counter/timers 24 macrocells decode pld (dpld) figure 1. psd5xx block diagram
psd5xx family 6-4 general description (cont.) at the core of the psd5xx are dedicated zplds based on the functions they perform: o decoding zpld (dpld) o general purpose zpld (gpld) o peripheral zpld (ppld) all zplds receive the same inputs through the zpld bus and are differentiated by their output destinations. the decoder pld (dpld ) has as its main function to perform address space decoding for the internal i/o ports, peripherals, four blocks of eprom, standby sram and peripheral mode of port a. the address decoding can be based on any address input, control signal (rd, psen, etc.) and page logic. address inputs originate from either the microcontroller interface (adio port) or other i/o ports for additional decoding. the dpld also supports special requirements of 8031 architecture based designs that need to store data in the eprom or execute programs from the sram. the general purpose pld (gpld) is a general purpose zpld that can be used to implement state machines and logic . the gpld has up to 61 inputs, 118 product terms, 24 flexible macrocells and 24 i/o pins that are connected to ports a, b and e. the gpld can also decode the microcontroller address bus and generate chip selects to external peripherals or memories. the peripheral pld (ppld) generates outputs to the counter/timer unit and the interrupt controller. the ppld outputs to the counter/timer enable, disable or trigger counting or time capture. this unique capability enables the user to implement in the ppld the exact conditions for the timer to count or generate an output. the ppld also generates four outputs to the interrupt controller which enables the user to define the exact conditions for interrupt generation. the zplds are designed to consume minimum power using zero power design techniques. a configuration bit (turbo bit), that can be set by the mcu, will automatically place the zplds into standby if no inputs are changing. any unused product terms will be turned off during programming and will not consume any power in the system. the psd5xx has 40 i/o pins that are divided into 5 ports. each i/o pin can be individually configured to provide many functions. ports a, b and e have the capability to be configured as standard mcu i/o ports, gpld i/o, latched address outputs for multiplexed address/data controllers, or special function i/o (e. g., counter/timer and interrupts). ports c and d are standard i/o ports that can also be configured as zpld inputs or data bus for microcontrollers with non-multiplexed bus. the psd5xx can easily interface with no ?lue-logic?to a variety of 8 and 16-bit microcontrollers with a multiplexed or non-multiplexed bus. all of the control signals are connected to the three zplds enabling the user to generate timing and decoding signals for external peripherals. for controllers that do not have a reset output, the psd5xx can generate a reset output based on its reset input that includes hysteresis. the counter/timer unit provides four 16 bit highly flexible counter/timers. each counter/timer has five modes of operation: pulse, waveform, event counting, time capture and watchdog (real time clock). counter 2 can operate as a watch dog timer. each counter/timer can be programmed to count up or down. the inputs to the counter/timer unit, which enable/disable counting or triggering an operation, can originate from the ppld or directly from the pins. the maximum operating frequency of each counter is 7.5 mhz. the input clock can be divided (up to 280) before driving the counter/timer unit using the 4 to 280 range prescaler .
psd5xx family 6-5 general description (cont.) the psd5xx includes an 8 level priority encoded interrupt controller. the interrupt controller accepts 4 user defined interrupts and 4 terminal counts from the counter/timer. each interrupt can be individually masked and configured to be level or edge sensitive. a 3 bit interrupt vector is generated that can be read by the microcontroller. the serviced interrupt will be cleared automatically after the microcontroller has read the interrupt vector. the psd5xx contains eprom and scratchpad sram. the eprom densities are 256k, 512k bit and 1m bit and are divided into four blocks. each block can be located in a different address location. the access time of the eprom includes the address latching and dpld decoding. the 16 kbit standby sram may be used as an extension of the microcontroller sram and also to store backup information that is necessary after a system power down or power failure. power to the sram is supplied by the vstby pin. switching between v cc and vstby occurs automatically when v cc power is removed. a four bit page register enables microcontrollers with limited address space easy access to the i/o section, eprom and sram . the page register outputs are connected to all zplds and can be used to page external devices as well as the internal psd5xx functional units. a power management unit (pmu) in the psd5xx enables the user to control the power consumption on selected functional blocks based on system requirements. for microcontrollers that do not generate a chip select input (csi) to the peripheral device, the pmu includes an automatic power down unit (apd) that will turn off the psd5xx (into standby or sleep mode) based on inactivity of the ale. the polarity of ale inactivity can be defined by the user. in addition to power down mode, the psd5xx includes a sleep mode that will reduce the power consumption to 10 a. the psd5xx family is supported by the psd development system (psdsoft, see figure 2) which runs under ms-windows on the pc. design entry is done using psdabel which creates a minimized logic implementation. psdabel also provides logic simulation of the zpld. the psd5xx desired configuration is entered using a simple window based menu. the psd compiler, which consists of a fitter and address translator, generates an object file from the psdabel and mcu code files. the object file can be down loaded to a programmer (magicpro , data i/o or other third party) or to psdsilos iii providing full chip simulation. the psd5xx standard versions include up to 1 mb of eprom, 16 kbit sram, decode pld (dpld), general purpose pld (gpld), peripheral pld (ppld), four 16-bit counter/timers, an 8-level maskable interrupt controller and five 8-bit i/o ports. they are ideal for general purpose embedded systems applications. the psd5xxm mask-programmable versions deliver the lowest cost psd5xx solution. see the masked-psd ordering information chapter in this databook for the mask-programmable psd5xxm ordering procedure. references in this document to psd5xx versions are generic and include psd5xx and psd5xxm products.
psd5xx family 6-6 figure 2. psdsoft development tools psdsilos iii silosiii chip simulation psd programmer magicpro chip programming psd compiler (zpld fitting, address translation) ms ?windows editor: .abl file psdabel zpld description (state machine, decoding) psd configuration chip configuration third party programmers code file psd5xx family there are 6 unique devices in the psd5xx family. the part classifications are based on eprom size and data bus width. the features of each part are listed in table 1. part bus dpld + gpld + ppld i/o timers inter. wd * pmu eprom sram # bit inputs product registered pins contr. k bit k bit terms macrocells 501b1 x8/x16 61 140 30 40 4 * 16 8 1 * 16 yes 256 16 511b1 x8 61 140 30 40 4 * 16 8 1 * 16 yes 256 16 502b1 x8/x16 61 140 30 40 4 * 16 8 1 * 16 yes 512 16 512b1 x8 61 140 30 40 4 * 16 8 1 * 16 yes 512 16 503b1 x8/x16 61 140 30 40 4 * 16 8 1 * 16 yes 1024 16 513b1 x8 61 140 30 40 4 * 16 8 1 * 16 yes 1024 16 table 1. psd5xx product matrix wd = watchdog timer. pmu = power management unit. * one of the four 16-bit timers.
psd5xx family 6-7 table 2. psd5xx pin descriptions pin name pin function type function descriptions adio0 ?adio15 address/ data bus i/o 1. address/data bus, multiplexed bus mode 2. address bus, non-multiplexed bus mode rd multiple names i multiple functions 1. read 1. read signal 2. e 2. e signal (clock) 3. ds 3. data strobe signal 4. lds 4. low byte data strobe wr multiple names i multiple functions 1. wr 1. write signal 2. r/w 2. read-write signal 3. wrl 3. low byte write signal csi chip select input i active low, select psd5xx. standby mode if high. reset reset input i reset i/o ports, zpld/macrocells, timers and configuration registers. active low. clkin input clock i clock input to timers, zpld macrocells, zpld array, and apd counter; connect to ground if clock input not used. pa0 ?pa7 i/o port a i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pa0?a7) ? (a0?7) 4. high address inputs (a16 ?a23) 5. timer outputs (pa0 ?pa3) pb0 ?pb7 i/o port b i/o multiple functions 1. i/o port 2. zpld/macrocell i/o port 3. latched address outputs (pb0?b7) ? (a0?7) or (a8?15) 4. timer outputs (pb0-pb3) pc0 ?pc7 i/o port c i/o multiple functions cmos 1. i/o port or 2. zpld input port od 3. latched address outputs (pc0 ?pc7) ? (a0?7) 4. data port (d0 ?d7, non-multiplexed bus) pd0 ?pd7 i/o port d i/o multiple functions cmos 1. i/o port or 2. zpld input port od 3. latched address outputs (pd0?d7) ? (a0?7) or (a8?15) 4. data port (d8-d15, non-multiplexed bus) the following table describes the pin names and pin functions of the psd5xx. pins that have multiple names and/or functions are defined by user configuration.
pin name pin function type function descriptions pe0 port pe, pin 0 i/o multiple functions 1. bhe 1. high byte enable, 16 bit data 2. psen 2. read program memory, 8031 signal 3. wrh write high data byte 4. uds 4. upper data strobe 5. siz0 5. byte enable, 68300 signal 6. pe0 6. i/o pin 7. pe0 7. zpld i/o pin 8. pe0 8. latched address out ?a0 pe1 port pe, pin 1 i/o multiple functions 1. ale 1. address strobe 2. pe1 2. i/o pin 3. pe1 3. zpld i/o pin 4. pe1 4. latched address out ?a1 pe2 port pe, pin 2 multiple functions 1. intr out 1. interrupt controller output 2. pe2 i/o 2. i/o pin 3. pe2 3. zpld i/o pin 4. pe2 4. latched address out ?a2 pe3 port pe, pin 3 multiple functions 1. timer0-in 1. timer0 control input 2. pe3 i/o 2. i/o pin 3. pe3 3. zpld i/o pin 4. pe3 4. latched address out ?a3 pe4 port pe, pin 4 multiple functions 1. timer1-in 1. timer1 control input 2. pe4 i/o 2. i/o pin 3. pe4 3. zpld i/o pin 4. pe4 4. latched address out ?a4 5. tc0 5. timer0 terminal count pe5 port pe, pin 5 multiple functions 1. timer2-in 1. timer2 control input 2. pe5 i/o 2. i/o pin 3. pe5 3. zpld i/o pin 4. pe5 4. latched address out ?a5 5. tc1 5. timer1 terminal count pe6 port pe, pin 6 multiple functions 1. timer3-in 1. timer3 control input 2. pe6 i/o 2. i/o pin 3. pe6 3. zpld i/o pin 4. pe6 4. latched address out ?a6 5. tc2 5. timer2 terminal count pe7 port pe, pin 7 multiple functions 1. apd clk 1. automatic power down clock input 2. pe7 i/o 2. i/o pin 3. pe7 3. zpld i/o pin 4. pe7 4. latched address out ?a7 5. tc3 5. timer3 terminal count vstby vstby i sram power pin for standby operation (battery backup) v cc v cc i chip v cc power pin gnd gnd i chip ground pin psd5xx family 6-8 table 2. psd5xx pin descriptions (cont.)
psd5xx family 6-9 the psd5xx architecture psd5xx consists of seven major functional blocks: o zpld block o bus interface o i/o ports o memory block o power management unit o counter/timer o interrupt controller the functions of each block are described in the following sections. many of the blocks perform multiple functions, and are user configurable. the chip configurations are specified by the user in the psdsoft development software; some are specified by setting up the appropriate bits in the configuration registers during run time. zpld block key features o 3 embedded zpld devices o maximum 30 macrocells o combinatorial/registered outputs o maximum 140 product terms o programmable output polarity o user configured register clear/preset o user configured register clock input o 61 inputs o accessible via 24 i/o pins o power saving mode o uv-erasable o generate user defined interrupts to interrupt controller and controls to counter/ timer general description the zpld block has 3 embedded pld devices: o dpld the address decoding pld, generating select signals to internal i/o or memory blocks. o gpld the general purpose pld provides 24 programmable macrocells for general or complex logic implementation; dedicated to user application. o ppld the peripheral pld, includes 6 programmable macrocells. the ppld provides control to the operation of the counter/timer and interrupt controller. figure 3 shows the architecture of the zpld. the pld devices all share the same input bus. the true or complement of the 61 input signals are fed to the programmable and-array. names and source of the input signals are shown in table 3. the pa, pb, pe signals, depending on user configuration, can either be macrocell feedbacks or inputs from port a, b or e.
psd5xx family 6-10 figure 3. zpld block diagram page reg. adio port prog. port port c prog. port port d pmu csi rd/ e/ds wr / r_w reset clkin pgr0 ?3 a8 ?a15 a0, a1 pc0 ?pc7 pd0 ?pd7 intr2pld and array and array and array and array and array dpld es0 ?es3 rs0 csiop psel0 ?psel1 8 i /o macrocells pa 8 i /o macrocells pb 8 i /o macrocells pe 4 output 4 output macrocells 2 output macrocells 27 pt 80 pt 11 pt 8 pt 4 pt 2 pt pt2int4 ?5 mc2int6 ?7 mc2tmr0 ?3 pe0 ?pe7 pb0 ?pb7 pa0 ?pa7 prog. port port a prog. port port b prog. port port e timers intr. ctrl dpld gpld ppld zpld input bus (decoding pld) (general purpose pld) (peripheral pld) wdog2pld zpld block (cont.)
psd5xx family 6-11 signal name from pa0 ?pa7 port a inputs or macrocell pa feedback pb0 ?pb7 port b inputs or macrocell pb feedback pe0 ?pe7 port e inputs or macrocell pe feedback pc0 ?pc7 port c inputs pd0 - pd7 port d inputs pgr0 ?pgr3 page mode register wdog2pld counter/timer intr2pld interrupt controller a8 ?a15, a0, a1 mcu address lines rd/e/ds mcu bus signal wr/r_w mcu bus signal clkin input clock reset reset input csi csi input (ored with power down from pmu) table 3. zpld input signals zpld block (cont.)
psd5xx family 6-12 the dpld the dpld is used for internal address decoding generating the following eight chip select signals: o es0 ?es3 eprom selects, block 0 to block 3 o rs0 sram block select o csiop i/o decoder chip select o psel0 ?psel1 peripheral i/o mode select signals the i/o decoder enabled by the csiop generates chip selects for on-chip registers or i/o ports based on address inputs a[7:0]. as shown in figure 4, the dpld consists of a large programmable and array. there are a total of 61 inputs and 8 outputs. each output consists of a single product term. although the user can generate select signals from any of the inputs, the select signals are typically a function of the address and page register inputs. the select signals, which are active high, are defined by the user in the abel file (psdabel). the address line inputs to the dpld include a0, a1 and a8 ?a15. if more address lines are needed, the user can bring in the lines through port a to the dpld. the gpld the structure of the general purpose pld consists of a programmable and array and 3 sets of i/o macrocells. the array has 61 input signals, same as the dpld. from these inputs, ?nded?functions are generated as product term inputs to the macrocells. the i/o macrocell sets are named after the i/o ports they are linked to, e.g., the macrocells connected to port a are named pa macrocells. the 3 sets of macrocells, pa, pb and pe, are similar in structure and function. figure 5 shows the output/input path of a gpld macrocell to the port pin with which it is associated. if the port pin is specified as a gpld output pin in psdsoft, the mux in the i/o port cell selects the gpld macrocell as an output of the port pin. the output enable signal to the buffer in the i/o cell can be controlled by a product term from the and array. if the port pin is specified as a zpld input pin, the mux in the gpld macrocell selects the port input signal to be one of the 61 signals in the zpld input bus. zpld block (cont.)
psd5xx family 6-13 figure 4. dpld logic array pa0 ?pa7 (8) (8) (8) (8) (8) (4) (10) (2) (3) (1) (1) (inputs) pb0 ?pb7 pe0 ?pe7 pc0 ?pc7 pd0 ?pd7 pgr0 ?pgr3 a8 ?a15, a0, a1 wdog2pld intr2pld csi, clkin reset rd/e/ds wr /r_w es0 es1 es2 es3 rs0 csiop psel0 psel1 4 eprom block selects ram select i /o decoder select peripheral i /o selects dpld inputs : 61 dpld outputs : 8 zpld block (cont.)
psd5xx family 6-14 zpld block (cont.) port a macrocell structure figure 5a shows the pa macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port a. there are 3 user programmable global product terms output from the gplds and array which are shared by all the macrocells in port a: o pa.oe enable or tri-state port a output pins o pa.pr preset d flip flop in the macrocells o pa.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a port a macrocell is shown in figure 6. there are 6 product terms from the gplds and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port a pin as dedicated input o gpld output use port a pin as dedicated output o gpld i/o use port a pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port a pin, port a can be configured to perform other user defined i/o functions. the two global product terms assigned for asynchronous clear (pa.re) and preset (pa.pr) are mainly for proper port a macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst, if such an option is chosen. the clock source is always the input clock clkin.
psd5xx family 6-15 dq figure 5 and array polarity select cl ck pr control clk select mux pt clock pt output enable (oe) pt reset gpld macrocell i/o port cell pt clear clkin macro_rst global clock port pin comb./reg. select gpld macrocell output internal address/data/control bus zpld input bus mux mux mux pcr d d q q wr direction register dq wr d g q ale pdr port input input output address a[0-7] or a[8-15] gpld output special function pts latch ale 60 * * = latch only on port a figure 5. gpld macrocell input/output port zpld block (cont.)
and array mc0 pa0 mc1 pa1 mc7 pa7 macro. out pa0 input macro. out pa1 input macro. out pa7 input pt [ 2:0 ] pa0 pt [ 2:0 ] pa1 pt [ 2:0 ] pa7 pa.pr pa.re pa.oe clkin macro rst port a i/o cells pa macrocell psd5xx family 6-16 figure 5a. pa macrocell block diagram zpld block (cont.)
psd5xx family 6-17 dq pt pt pt pt pt pt and array polarity select pld in select c pr mux mux pa .oe pa.pr pt0 pt1 pt2 pa .re pai macro rst note: i = 7 to 0 clkin macro . out i/o pin pai port a comb / reg select internal address/data bus pai input zpld bus figure 6. pa macrocell zpld block (cont.)
psd5xx family 6-18 port b macrocell structure figure 7 shows the pb macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port b. the two inputs, clkin and macro-rst, are used as clock and clear inputs to all the macrocells. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pb macrocell is shown in figure 8. there are 10 product terms from the gplds and array as inputs to the macrocell. users can select the polarity of the output, and configure the macrocell to operate as: o registered output select output from d flip flop. o combinatorial output select output from or gate. o gpld input use port b pin as dedicated input. o gpld output use port b pin as dedicated output. o gpld i/o use port b pin as bidirectional pin. o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to a port b pin, port b can be configured to perform other user defined i/o functions. each d flip flop in the macrocells has its own dedicated asynchronous clear, preset and clock input. the signals are defined as follow: o preset active only if defined by a product term (pbx.pr) o clear two selectable inputs: reset input or user defined product term (pbx.re) o clk two selectable inputs ? clkin input or user defined product term (pbx.clk). the macrocell is operated in synchronous mode if the clock input is clkin, and is in asynchronous mode if the clock is a product-term clock defined by the user. zpld block (cont.)
psd5xx family 6-19 and array macro .out pb0 .oe pb0 ?input macro .out pb1 .oe pb1 input macro .out pb7 .oe pb7?input ptb0 ? [ 0 . . 5 ] pb0 .pr pb0 .re pb0 .oe pb0 .clk pb0 ptb1 ? [ 0 . . 5 ] pb1 .pr pb1 .re pb1 .oe pb1 .clk pb1 ptb7 ? [ 0 . . 5 ] pb7 .pr pb7 .re pb7 .oe pb7 .clk pb7 clkin macro ?rst port b i/o cells pb macrocell mc0 mc1 mc7 pb0 pb1 pb7 figure 7. pb macrocell block diagram zpld block (cont.)
psd5xx family 6-20 dq pt pt pt pt pt pt pt pt pt pt and array polarity select comb /reg select c pr mux pld in select mux clk select mux pbi pbi .oe pbi .pr pt0 pt1 pt2 pt3 pt4 pt5 pbi .clk pbi .re macro rst clkin macro . out i /o pin pbi port b internal address /data bus pbi ?input note: i = 7 to 0 zpld bus figure 8. pb macrocell zpld block (cont.)
psd5xx family 6-21 zpld block (cont.) port e macrocell structure figure 9 shows the pe macrocell block, which consists of 8 identical macrocells. each macrocell output can be connected to its own i/o pin on port e. there are 3 user programmable global product terms output from the gplds and array which are shared by all the macrocells in port e: o pe.oe enable or tri-state port pe output pins o pe.pr preset d flip flop in the macrocells o pe.re reset/clear d flip flop in the macrocells two other inputs, clkin and macro-rst, are used as clock and clear inputs to the d flip flop. the clkin comes directly from the clkin input pin. the macro-rst is the same as the reset input pin except it is user configurable. the circuit of a pe macrocell is shown in figure 10. there are 4 product terms from the gplds and array as input to the macrocell. users can select the polarity of the output and configure the macrocell to operate as: o registered output select output from d flip flop o combinatorial output select output from or gate o gpld input use port e pin as dedicated input o gpld output use port e pin as dedicated output o gpld i/o use port e pin as bidirectional pin o macrocell feedback register feedback for state machine implementations or expander feedback from the combinatorial output, to possibly expand the number of product terms available to another macrocell. in case of "buried feedback", where the output of the macrocell is not connected to port e pin, port e can be configured to perform other user defined i/o functions. if pins pe0 and pe1 are used as bus control signal inputs (ale, psen/bhe), the corresponding macrocells' feedbacks are disabled. the bus control signals are connected to the zpld input bus. the two global product terms assigned for asynchronous clear (pe.re) and preset (pe.pr) are mainly for proper pe macrocell initialization. the macrocell flip-flop can also be cleared during reset by macro-rst, if such an option is chosen. the clock source is always the input clock clkin.
psd5xx family 6-22 figure 9. pe macrocell block diagram and array mc0 pe0 mc1 pe1 mc7 pe 7 macro .out pe0 ?input macro .out pe1 ?input macro .out pe7?input pt pe0 pt pe1 pt pe7 pe .pr pe .re pe .oe clkin macro ?rst port e i/o cells pe macrocell zpld block (cont.)
psd5xx family 6-23 figure 10. pe macrocell dq pt pt pt pt and array polarity select pld in select c pr mux mux pe .oe pe .pr pt pe .re pei macro rst note: i = 7 to 0 clkin macro .out i/o pin pei port e internal address/data bus pei input comb / reg select zpld bus zpld block (cont.)
psd5xx family 6-24 the ppld the peripheral programmable logic device (ppld) provides a powerful mechanism for the user to control the operations of the counter/timer and interrupt controller. figure 11 is the ppld block diagram. there are six peripheral macrocells, four are dedicated to the counter/timer, and two to the interrupt controller. the outputs from the four peripheral macrocells, mc2tmr[3:0], are used as load/store/enable inputs to the counter/timer (multiplexed with pin inputs timer[3:0] _in). the remaining two macrocell outputs (mc2int[6:7] ), together with two other product terms (pt2int4, pt2int5), can generate up to 4 user defined interrupts to the interrupt controller. the watch-dog output of the timer (wdog2pld) and interrupt controller (intr2pld) are available as inputs to the zplds and array. the structure of a peripheral macrocell is shown in figure 12. the cell has two product term inputs from the and array. the user can select the registered or combinatorial output of the macrocell, as well as the output polarity. the registers are clocked by the clkin clock, and are cleared by the reset input during power up. the zpld power management the zpld implements a zero power mode, which provides considerable power savings for low to medium frequency operations. to enable this feature, the zpld turbo bit in the power management mode register 0 (pmmr0) has to be turned off. if none of the 61 inputs to the zpld are switching for a time period of 70ns, the zpld puts itself into zero power mode and the current consumption is minimal. the zpld will resume normal operation as soon as one or more of the inputs change state. two other features of the zpld provide additional power savings: 1. clock disable: users can disable the clock input to the zpld and/or macrocells, thereby reducing ac power consumption. 2. product term disable: unused product terms in the zpld are disabled by the psdsoft software automatically for further power savings. the zpld power configuration is described in the power management unit section. zpld block (cont.)
psd5xx family 6-25 figure 11. ppld block diagram port e macrocells (4) macrocells (2) counter/ timer interrupt controller and array timer [ 3 : 0 ] in tc [ 3 : 0 ] tc [ 3 : 0 ] mc2tmr [ 3 : 0 ] wdog2pld intr2pld pt2int4 pt2int5 mc2int6 mc2int7 pt (8) pt (4 ) pt pt mux zpld block (cont.)
psd5xx family 6-26 figure 12. peripheral macrocell dq pt pt and array polarity select comb /reg select c mux pt0 pt1 clkin reset to timer or interrupt controller zpld bus the zpld block (cont.)
psd5xx family 6-27 bus interface the bus interface is very flexible and can be configured to interface to most microcontrollers with no glue logic. table 4 lists some of the bus types to which the bus interface is able to interface. multiplexed data bus bus control microcontroller width signals mux 8 wr, rd, psen, a0 8031 mux/ non-mux 8/16 r/w, e, bhe, a0 6811 mux 8/16 wr, rd, bhe, a0 80196/80186 mux 16 wrl, rd, wrh, a0 80196sp non-mux 16 r/w, lds, uds 68302 non-mux 8/16 r/w, ds, siz0, a0 68340 non-mux 16 r/w, ds, bhe, ble 68330 table 4. typical microcontroller bus types bus interface configuration the bus interface logic is user configurable. the type of bus interface is specified by the user in the psdsoft software (psd configuration). the bus control input pins have multi-function capabilities. by choosing the right configuration, the psd5xx is able to interface to most microcontrollers, including the ones listed in table 4. in table 5, the names of the bus control input signal pins and their multiple functions are shown. for example, pin pe0 can be configured by the psd configuration software to perform any one of the five functions. examples on the interface between the psd5xx and some typical microcontrollers are shown in following sections. pin name pin pin pin pin pin function function function function function 12345 rd rd e ds lds wr wr r/w wrl pe0 bhe psen wrh uds siz0 pe1 ale ad0 a0 ble table 5. alternate pin functions psd5xx interface to a multiplexed bus figure 13 shows a typical connection to a microcontroller with a multiplexed bus. the adio port of the psd5xx is connected directly to the microcontroller address/data bus (ad0-ad15 for 16 bit bus). the ale input signal latches the address lines internally. in a read bus cycle, data is driven out through the adio port transceivers after the specified access time. the internal adio port connection for a 16 bit multiplexed bus is shown in figure 14. the adio port is in tri-state mode if none of the psd5xx internal devices are selected.
psd5xx family 6-28 psd5xx interface to non-multiplexed bus figure 15 shows a psd5xx interfacing to a microcontroller with a non-multiplexed address/data bus. the address bus is connected to the adio port, and the data bus is connected to port c and/or port d, depending on the bus width. there is no need for the adio port to latch the address internally, but the user is offered the option to do so in the psd5xx psdsoft software. the data ports are in tri-state mode when the psd5xx is not accessed by the microcontroller. bus interface (cont.) data byte enable microcontrollers have different data byte orientations with regard to the data bus. the following tables show how the psd5xx handles the byte enable under different bus configurations. even byte refers to locations with address a0 equal to ?? and odd byte as locations with a0 equal to ?? bhe a0 d7 ?d0 x 0 even byte x 1 odd byte table 6. 8-bit data bus table 7. 16-bit data bus with bhe bhe a0 d15 ?d8 d7 ?d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte wrh wrl d15 ?d8 d7 ?d0 0 0 odd byte even byte 0 1 odd byte 1 0 even byte table 8. 16-bit data bus with wrh and wrl siz0 a0 d15 ?d8 d7 ?d0 0 0 even byte odd byte 1 0 even byte 1 1 odd byte table 9. 16-bit data bus with siz0, a0 lds uds (a0) d15 ?d8 d7 ?d0 0 0 even byte odd byte 1 0 even byte 0 1 odd byte table 10. 16-bit data bus with uds, lds
psd5xx family 6-29 figure 13. bus interface ? multiplexed bus, 8 or 16-bit data bus micro- controller ad ? [ 7:0 ] ad ? [ 15 : 8 ] ( a ? [ 15 : 8 ] ) a ? [ 7:0 ] a ? [ 15 : 8 ] (optional) (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd5xx bus interface (cont.)
ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 adio? adio? adio? adio? adio? adio? adio? adio? adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 r_w ale /as psd5xx internal address bus psd5xx internal data bus latch g latch g psd5xx family 6-30 figure 14. adio port, 16-bit multiplexed bus interface bus interface (cont.)
psd5xx family 6-31 figure 15. bus interface ? non-multiplexed, 8 or 16-bit data micro- controller d ? [ 15 : 0 ] a ? [ 15 : 0 ] d ? [ 15 : 8 ] d ? [ 7 : 0 ] a [ 23 :16 ] (optional) adio port port e wr rd rst csi bhe ale port c port d port a port b psd5xx 16-bit data only bus interface (cont.)
psd5xx family 6-32 optional features the psd5xx provides two optional features to add flexibility to the bus interface: 1. address in port a can be configured as high order address (a16-a23) inputs to the zpld for eprom or other decoding. inputs are latched by ale/as if multiplexed bus is selected. other ports can be configured as address input ports for the zpld. these inputs should not be used for eprom decoding and are not latched internally. 2. address out for multiplexed bus only. latched address lines a0-a15 are available on port a, b, c, d, or e. details on the optional features are described in the i/o port section. bus interface (cont.) bus interface examples the next four figures show the psd5xx interfacing with some popular microcontrollers. the examples show only the basic bus connections; some of the pin names on the psd5xx parts change to reflect the actual pin functions. figure 16 shows an interface to the 80c31. the 80c31 has a 16 bit address bus and an 8-bit data bus. the lower address byte is multiplexed with the data bus. the rd and wr signals are used for accessing the data memory (sram) and the psen signal is for reading program memory (eprom). the ale signal is active high and is used to latch the address internally. port c provides latched address outputs a[7:0]. ports a, b, d, and e (pe2-pe7) can be configured to perform other functions. the rstout reset to the 80c31 is generated by the zpld from the reset input. this configuration eliminates any reset race condition between the 80c31 and the psd5xx. figure 17 shows the 68hc11 interface, which is similar to the 80c31 except the psd5xx generates internal rd and wr from the 68hc11s e and r/w signals. in figure 18, the intel 80c196 microcontroller is interfaced to the psd5xx. the 80c196 has a multiplexed 16-bit address and data bus. the bhe signal is used for data byte selection. ports c and d are used as output ports for latched address a[15:0]. pins pe6 and pe7 can be programmed as zpld outputs to provide the ready and buswidth control signals to the 80c196. figure 19 shows motorolas mc68331 interfacing to the psd5xx. the mc68331 has a 16-bit data bus and a 24-bit address bus. d15-d8 from the mc68331 are connected to port d, and d7 ?d0 are connected to port c.
psd5xx family 6-33 figure 16. interfacing psd5xx with 80c31 ea / vp x1 x2 reset int0 int1 t0 t1 p1 . 0 p1 . 1 p1 . 2 p1 . 3 p1 . 4 p1 . 5 p1 . 6 p1 . 7 ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / psen pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd wr psen ale/p txd rxd pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 80c31 ad [ 7:0 ] ad [ 7:0 ] reset rstout clock reset clock psd5xx rd wr psen ale bus interface (cont.)
psd5xx family 6-34 figure 17. interfacing psd5xx with 68hc11 xt ex reset irq xirq modb pa0 pa1 pa2 pe0 pe1 pe2 pe3 pe4 pe5 pe6 pe7 vrh vrl ad0 /a0 ad1/a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11/a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 e r/w reset csi clkin pe0 pe1 / ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 moda e as r/w pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 8 7 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 68hc11 reset psd5xx ad [ 7 : 0 ] ad [ 7 : 0 ] clock reset e ale r/w clock ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 bus interface (cont.)
psd5xx family 6-35 figure 18. interfacing psd5xx with 80c196 x1 nmi ready cde buswidth reset ach0 / p0 . 0 ach1 / p0 . 1 ach2 / p0 . 2 ach3 / p0 . 3 ach4 / p0 . 4 ach5 / p0 . 5 pcs6 / p0 . 6 pcs7/ p0 . 7 p2 . 0 / txd p2 . 1 / rxd p2 . 2 / exint p2 . 3 / t2clk p2 . 4 / t2rst p2 . 5 / pwm p2 . 6 / t2up ?dn p2 . 7/ t2cap hsi .0 hsi .1 hsi .2 / hso .4 hsi .3 / hso .5 vref angnd ea? ad0 /a0 ad1 /a1 ad2 /a2 ad3 /a3 ad4 /a4 ad5 /a5 ad6 /a6 ad7/a7 ad8 /a8 ad9 /a9 ad10 /a10 ad11 /a11 ad12 /a12 ad13 /a13 ad14 /a14 ad15 /a15 rd wr reset csi clkin pe0 / bhe pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby x2 p3 . 0 /ad0 p3 . 1 /ad1 p3 . 2 /ad2 p3 . 3 /ad3 p3 . 4 /ad4 p3 . 5 /ad5 p3 . 6 /ad6 p3 . 7/ad7 p4 . 0 /ad8 p4 . 1 /ad9 p4 . 2 /ad10 p4 . 3 /ad11 p4 . 4 /ad12 p4 . 5 /ad13 p4 . 6 /ad14 p4 . 7/ad15 rd wr bhe ale inst clkout p1 .0 p1 .1 p1 .2 p1 .3 p1 .4 p1 .5 p1 .6 p1 .7 hso .0 hso .1 hso .2 hso .3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 11 3 43 14 64 16 6 5 7 4 11 10 8 9 18 17 15 44 42 39 33 38 24 25 26 27 13 12 2 12 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 61 40 41 62 63 65 59 58 57 56 55 48 47 46 50 49 44 43 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] reset ready buswidth rd wr bhe ale clkout psd5xx 80c196 bus interface (cont.)
psd5xx family 6-36 figure 19. interfacing psd5xx with motorola 68331 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 reset dsack0 dsack1 irq1 irq2 irq3 irq4 irq5 irq6 irq7 ad0 / a0 ad1 / a1 ad2 / a2 ad3 / a3 ad4 / a4 ad5 / a5 ad6 / a6 ad7 / a7 ad8 / a8 ad9 / a9 ad10 / a10 ad11 / a11 ad12 / a12 ad13 / a13 ad14 / a14 ad15 / a15 ds r / w reset csi clkin pe0 / siz0 pe1 /ale pe2 pe3 pe4 pe5 pe6 pe7 vstdby a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 cs6 a20 cs7 a21 cs8 a22 cs9 a23 cs10 as r w ds siz0 siz1 clkout csboot brcs0 bgcs1 bgackcs2 fc0cs3 fc1cs4 fc2cs5 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 d0 111 d1 110 d2 109 d3 108 d4 105 d5 104 d6 103 d7 102 d8 100 d9 99 d10 98 d11 97 d12 94 d13 93 d14 92 d15 91 68 89 88 77 76 75 74 73 72 71 90 20 21 22 23 24 25 26 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 82 79 85 81 80 66 112 113 114 115 118 119 120 17 16 15 14 13 12 11 10 60 59 58 57 56 55 54 53 27 26 25 24 23 22 21 20 50 49 48 47 46 45 44 43 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 ale rw ds siz0 clkout d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61 41 29 40 39 42 38 37 36 34 33 32 31 30 28 reset d [ 15 : 0 ] d [ 15 : 0 ] a [ 18 : 0 ] a [ 18 : 0 ] reset psd5xx mc68331 bus interface (cont.)
psd5xx family 6-37 there are 5 programmable 8-bit i/o ports: port a, port b, port c, port d and port e. these ports all have multiple operating modes, depending on the configuration. some of the basic functions are providing input/output for the zpld, the counter/timer, or can be used for standard i/o. each port pin is individually configurable, thus enabling a single 8-bit port to perform multiple functions. the i/o ports occupy 256 bytes of memory space as defined by ?siop? refer to the system configuration section for i/o register address offset. to set up the port configuration the user is required to: 1. define i/o port chip select (csiop) in the abel file. 2. initialize certain port configuration registers in the users program and/or 3. specify the configuration in the psd5xx psdsoft software. 4. unused input pins should be tied to v cc or gnd. the following is a description of the operating modes of the i/o ports. the functions of the port registers are described in later sections. standard mcu i/o the standard mcu i/o mode provides additional i/o capability to the microcontroller. in this mode, the ports can perform standard i/o functions such as sensing or controlling various external i/o devices. operation options of this mode are as follows: o configuration 1. declare pins or signals which are used as i/o in the abel file (psdsoft). 2. set the bit or bits in the control register to "1". 3. as output port write output data to data out register set direction register to output mode 4. as input port set direction register to input mode read input from data in register the port remains an output or input port as long as the direction register is not changed. pld i/o the pld i/o mode enables the port to be configured as an input to the zpld, or as an output from the gpld macrocell. the output can be tri-stated with a control signal defined by a product term from the zpld. this mode is configured by the user in the psd5xx psdsoft software, and is enabled upon power up. for a detailed description, see the section on the zpld. o configuration 1. declare pins or signals in the abel file (psdsoft) 2. write logic equations in the abel file. 3. psdcompiler maps the pld function to the psd. i/o ports
psd5xx family 6-38 address out for microcontrollers with a multiplexed address/data bus, the i/o ports in address-out mode are able to provide latched address outputs (a0 ?a15) to external devices. this mode of operation requires the user to: o configuration 1. declare the pins used as address line outputs in the abel file psdsoft. 2. write ??to the corresponding bit in the control register associated with each i/o port. 3. set the direction register to output mode. address in 1. for port a ? as other address line (a2 ?a7 and a16 ?a23) inputs to the dpld. additional address inputs included in the eprom decoding must come from port a. the address inputs are latched internally by ale/as if multiplexed bus is specified in psdsoft. 2. for ports c and d ? as adress inputs to the zpld for general decoding, should not be used in eprom decoding. o configuration 1. declare pins or signals used as address in in the abel file (psdsoft). 2. write latch equations in the abl file, e.g., a16.le = ale 3. include latched address in logic equations. data port in this mode, the port is acting as a data bus port for a microcontroller which has a non-multiplexed address/data bus. in this configuration, the data port is connected to the data bus of the microcontroller and the adio port is connected to the address bus. o configuration select the non-multiplexed bus option in psd configuration (psdsoft). special function out this mode is per-pin configurable. when enabled, the special function assigned to the particular pin is driven out. special functions consist of timer and interrupt outputs. o configuration 1. specify the output function in the psd configuration (psdsoft). 2. psd compiler assigns pins for the selected function. 3. write ??to the corresponding bit in the special function register. i/o ports (cont.)
psd5xx family 6-39 alternate function in this mode is per-pin configurable and enables the user to define the pins in port e to perform alternate function. alternate function includes inputs to counter/timers and apd clock. o configuration 1. select input functions in psd configuration 2. psd compiler assigns pins for the selected function. peripheral i/o this mode enables the microcontroller to read or write to a peripheral though port a. when there is no read/write operation, port a is tri-stated. one of the applications of peripheral i/o is in a dma based design. o configuration 1. declare the pins used as peripheral i/o in the abel file. 2. write logic equations for psel0 and psel1. 3. write a ??to the pio bit in the vm register to activate the peripheral i/o operation. see the section on peripheral i/o for a detailed description. open drain outputs this mode enables the user to configure port c and d pins as open drain outputs. cmos output is the default configuration. writing ??to the corresponding bit in the open drain register changes the pin to open drain output. port mode port a port b port c port d port e standard mcu i/o yes yes yes yes yes pld i/o yes yes input only input only yes address out yes yes yes yes yes address in yes yes * yes * yes * yes * data port yes yes special function out yes yes yes alternate function in yes peripheral i/o yes open drain yes yes * for external decoding. cannot be latched by ale. table 11. operating modes of the i/o ports the following table summarizes the operating modes of the i/o ports. not all functions are available to every port. i/o ports (cont.)
psd5xx family 6-40 port registers there are two sets of registers per i/o port: the port configuration registers (pcr) which consist of four 8-bit registers; and the port data registers (pdr) which include three 8-bit registers. the pcr is used for setting up the port configuration, while the pdr enables the microcontroller to write or read port data or status bits. tables 12 and 13 show the names and the registers and the ports to which they belong. all the registers in the pcr and pdr are 8-bits wide and each bit is associated with a pin in the i/o port. in table 14, the lsb of the data in register of port a is connected to pin pa0, and the msb is connected to pa7. this pin configuration also applies to other registers and ports. for example, in the direction register of port a, writing a hex value of 07 to the register configures pins pa0 ?pa2 as output pins, while pa3 ?pa7 remain as input pins. registers can be accessed by the microcontroller during normal read/write bus cycles. the i/o address offset of the registers are listed in the system configuration section. i/o ports (cont.) register name port write/read control register a,b,c,d,e write/read direction register a,b,c,d,e write/read open drain register c,d write/read special function register a,b,e write/read pld ?i/o register a,b,e read table 12. port configuration registers (pcr) register name port read/write data in register a,b,c,d,e read data out register a,b,c,d,e write/read macrocell out register a,b,e read table 13. port data registers (pdr) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin table 14. data in register ?port a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pa7 pin pa6 pin pa5 pin pa4 pin pa3 pin pa2 pin pa1 pin pa0 pin = 0 = 0 = 0 = 0 = 0 = 1 = 1 = 1 direction register ?port a ( example: pins pa0 ?pa2 as output, pa3 ?pa7 as input)
psd5xx family 6-41 control register this register is used in both standard mcu i/o mode and address out modes. for setting a standard mcu i/o mode, a ??must be written to the corresponding bit in the register. writing a ??to the register is required for the address out mode. the register has a default value of ??after reset. direction register this register is used to control the direction of data flow in the i/o ports. writing a ??to the corresponding bit in the register configures the port to be an output port, and a ? forces the port to be an input port. the i/o configuration of the port pins can be determined by reading the direction register. after reset, the pins are in input mode. open drain register this register determines whether the output pin driver of port c or d is a cmos driver or an open drain driver. writing a ??to the register selects a cmos driver, while a ??selects an open drain driver. special function register writing a ??bit to this register sets up the corresponding pin to operate in special function out mode. pld ?i/o register this is a read only status register. reading a "1" indicates the corresponding pin is configured as a pld pin. a "0" indicates the pin is an i/o pin. data in register this register is used in the standard mcu i/o mode configuration to read the input pins. data out register this register holds the output data in the standard mcu i/o mode. the contents of the register can also be read. macrocell out register this register enables the user to read the outputs of the gpld macrocell (pa, pb, and pe macrocells). i/o register address offset the i/o register can be accessed by the microcontroller during normal read/write bus cycles. the address of a register is defined as: csiop + register address offset the csiop is the base address that is defined in the abel file and occupies a 256 byte space. the register address offset lies within this 256 byte space. tables 15 and 15a are the address offset of the registers. i/o ports (cont.)
psd5xx family 6-42 table 15a. register address offset (for 16-bit motorola microcontrollers in 16-bit mode. use table 15 if 8-bit mode is selected.) address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 special function 08 09 28 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c table 15. register address offset i/o ports (cont.) address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 special function 09 08 29 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d
psd5xx family 6-43 port a ? functionality and structure port a is the most flexible of all the i/o ports. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? latched address lines assigned to pins pa[0-7] o address in ? input port for other lines, inputs can be latched by ale. o special function out ? pins pa0 ?pa3 can be configured as dedicated timer outputs. o peripheral i/o figure 20 shows the structure of a port a pin. if the pin is configured as an output port, the multiplexer selects one of its four inputs as output. if the pin is configured as an input, the input connects to : 1. data in register as input in standard mcu i/o mode or 2. pa macrocell as pld input or 3. pa macrocell as address in input (latched for multiplexed bus). port b ? functionality and structure port b is similar to port a in structure. it can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? address lines a[0-7] for 8-bit multiplexed bus, or address lines a[8-15] for 16-bit multiplexed bus are assigned to pins pb[0-7]. o special function out ? pins pb0 - pb3 are configured as dedicated timer outputs. figure 21 shows the structure of a port b pin. if the pin is configured as an output port, the multiplexer selects one of its four inputs as output. if the pin is configured as input, the input connects to : o data in register as input in standard mcu i/o mode or o pb macrocell as pld input i/o ports (cont.)
psd5xx family 6-44 figure 20. port a pin structure mux pdr port a pin dq d g q dq control gpld input pcr ale wr ale pa . oe special func. gpld output ale wr internal address / data bus data out address pcr dir. reg. latch a [ 0 ?7 ] i/o ports (cont.)
psd5xx family 6-45 figure 21. port b pin structure mux pdr port b pin dq d g q dq control gpld input pcr wr ale pb .oe special func. gpld output ale wr internal address / data bus data out address pcr dir. reg. a[0 ?7] or a[8 ?15] i/o ports (cont.)
psd5xx family 6-46 port c and port d ? functionality and structure port c and d are identical in function and structure and each can be configured to perform one or more of the following operating modes: o standard mcu i/o mode o pld input ? direct input to zpld o address out ? latched address outputs port c: a[0-7] are asigned to pins pc[0-7] port d: a[0-7] for 8-bit multiplexed bus, or a[8-15] for 16-bit multiplexed bus are assigned to pins pd[0-7] o data port port c: d[0-7] for 8-bit non-multiplexed bus port d: d[8-15] for 16-bit non-multiplexed bus o open drain ? select cmos or open drain driver figures 22 and 23 show the structure of a port c or d pin. if the pin is configured as output port, the multiplexer selects one of the two inputs as output. if the pin is configured as input, the input connects to : o data in register as input in the standard mcu i/o mode or o zpld input port e ? functionality and structure port e can be configured to perform one or more of the following functions: o standard mcu i/o mode o pld i/o o address out ? latched address lines a[0-7] are assigned to pins pe[0-7]. o special function out ? in this mode, port e pin is configured as an output port for the following signals: pe2 interrupt ? interrupt output from interrupt controller pe4 terminal count output, timer0 pe5 terminal count output, timer1 pe6 terminal count output, timer2 pe7 terminal count output, timer3 o alternate function in ? in this mode, the inputs to port e pins are: pe0 bhe/ or psen/ or wrh/ or uds/ or siz0 pe1 ale pe3 timer0-in :load/store/enable/ disable input to timer 0 pe4 timer1-in :load/store/enable/disable input to timer 1 pe5 timer2-in :load/store/enable/disable input to timer 2 pe6 timer3-in :load/store/enable/disable input to timer 3 pe7 apd clk :clock input for automatic power down counter figure 24 shows the structure of a port e pin. the control logic block selects one of four sources through the multiplexer for pin output. if the pin is configured as input, the input goes to: o data in register as input in standard mcu i/o mode or o pe macrocell as pld input or o alternate function in i/o ports (cont.)
psd5xx family 6-47 figure 22. port c pin structure mux pdr port c pin dq d g q dq control gpld input * pcr wr ale ale wr data * internal address / data bus data out address pcr dir. reg. d [ 07 ] a [ 07 ] * data bus d [0?] is not connected to gpld?nput. i/o ports (cont.)
psd5xx family 6-48 figure 23. port d pin structure mux pdr port d pin dq d g q dq control gpld input * pcr wr ale ale wr data * internal address / data bus data out address pcr dir. reg. d [8 ?5] a [ 07 ] or a [8 ?5] * data bus d [8 ?5] is not connected to gpld?nput. i/o ports (cont.)
psd5xx family 6-49 figure 24. port e pin structure mux pdr port e pin dq d g q dq control gpld input alt func. in pcr wr ale pe . oe special func. gpld output ale wr internal address / data bus data out address pcr dir. reg. i/o ports (cont.)
psd5xx family 6-50 the psd5xx provides eprom memory for code storage and sram memory for scratch pad usage. chip selects for the memory blocks come from the dpld decoding logic and are defined by the user in the psdsoft software. figure 25 shows the organization of the memory block. eprom the psd5xx provides three eprom densities: 256k bit, 512k bit or 1m bit. the eprom is divided into four 8k, 16k or 32k byte blocks. each block has its own chip select signals (es0 ?es3). the eprom can be configured as 32k x 8, 64k x 8 or 128k x 8 for microcontrollers with an 8-bit data bus. for 16-bit data buses, the eprom is configured as 16k x 16, 32k x 16 or 64k x 16. sram the sram has 16k bits of memory, organized as 2k x 8 or 1k x 16. the sram is enabled by the chip select signal rs0 from the dpld. the sram has a battery back-up (stby) mode. this back-up mode is invoked when the v cc voltage drops under the vstby voltage by 0.6 v. the vstby voltage is connected only to the sram and cannot be lower than 2.7 volts. the sram data retention voltage is 2 volts. memory select map the eprom and sram chip select equations are defined in the abel file in terms of address and other dpld inputs. the memory space for the eprom chip select (es0 es3) should not be larger than the eprom block (8kb, 16kb or 32kb) it is selecting. the following rules govern how the internal psd5xx memory selects/space are defined: o the eprom blocks address space cannot overlap o sram, internal i/o and peripheral i/o space cannot overlap o sram, internal i/o and peripheral i/o space can overlap eprom space, with priority given to sram or i/o. the portion of eprom which is overlapped cannot be accessed. the peripheral i/o space refers to memory space occupied by peripherals when port a is configured in the peripheral i/o mode. memory block
psd5xx family 6-51 figure 25. memory block diagram (128kb eprom) es0 es1 es2 es3 16k x 8 16k x 8 1k x 8 1k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 16k x 8 sram block rs0 odd byte odd byte d [ 8 ?15 ] even byte d [ 0 ?7 ] eprom blocks memory block (cont.)
psd5xx family 6-52 memory select map for 8031 application the 8031 family of microcontrollers has separate code memory space and data memory space. this feature requires a different memory select map. two modes of operation are provided for 8031 applications. the selection of the modes is specified in the psd5xx psdsoft software (psdconfiguration): o separate space mode in this mode, the psen signal is used to access code from eprom, and the rd signal is used to access data from sram. the code memory space is separated from the data memory space. o combined space mode in this mode, the eprom can be accessed by psen or rd. the eprom is used for code and data storage. the memory block's address space cannot overlap. if data and code memory blocks must overlap each other, the rd signal can be included as an additional address input in generating the eprom chip select signals (es0 ?es3). in this case the eprom access time is from the rd valid to data valid. figures 26a and 26b show the memory configuration in the two modes. in some applications it is desirable to execute program codes in sram. the psd5xx provides this option by enabling psen to access sram. to activate this option, the srcode bit of the vm register must be set to ??(see table 16). sram space can overlap eprom space and has priority when psen is used. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** ** srcode pio 1 = on 1 = on * = reserved for future use, bits set to zero. table 16. vm register memory block (cont.)
psd5xx family 6-53 figure 26a. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 rd oe oe srcodeen psen separate space mode memory block (cont.) figure 26b. 8031 memory modes eprom dpld sram es0 es1 es2 es3 rs0 psen rd rd oe oe srcodeen psen rd combined space mode
psd5xx family 6-54 peripheral i/o the peripheral i/o mode is one of the operating modes of port a. in this mode, port a is connected to the data bus of peripheral devices. port a is enabled only when the microcontroller is accessing the devices, otherwise the port is tri-stated. this feature enables the microcontroller to access external devices without requiring buffers and decoders. figure 27 shows the structure of port a in the peripheral i/o mode. the memory address space occupied by the devices are defined by two signals: psel0 and psel1. the signals are direct outputs from the dpld. whenever any of the signals is active, the port a driver is enabled, and the direction of the data flow is determined by the rd/wr signals. the peripheral i/o mode and the peripheral select signals are configured and defined in the psdsoft software (see the section on i/o port for configurations). the pio bit in the vm register (see table 16) also needs to be set to ??by the user to initialize the peripheral i/o mode. the peripheral i/o mode can be used, for example, in dma applications where the microcontroller does not support dma operations, such as tri-stating the address/data bus. figure 28 shows a block diagram of a microcontroller and psd5xx based design that makes use of this mode. in this application, the microcontroller has a multiplexed bus which is connected to the adio port. the c and d ports connect to the peripheral address bus and are both configured in address out mode. port a is configured in the peripheral i/o mode and is connected to the peripheral data bus. port b and e are used to generate control signals. during normal activity, the microcontroller has access to any peripheral (memory or i/o device) through the psd5xx device. when there is a dma request, the microcontroller tri-states the address bus on port c and d by writing a ??to the port direction registers. the dma controller then takes over the data and address buses after receiving acknowledgement from the microcontroller. figure 27. port a in peripheral i/o mode rd psel0 psel1 d0 ?d7 wr pa0 ?pa7 peripheral i/o
psd5xx family 6-55 figure 28. psd5xx peripheral i/o configuration micro- controller ad [ 0 ?7 ] a [ 8 ?5 ] a [ 0 ?7 ] a [ 8 ?15 ] d [ 0 ?7 ] dma ack adio port port e wr rd rst csi bhe ale port c port d port a port b psd5xx memory i/o device dma controller peripheral # 1 peripheral # 2 dma req rd wr csi peripheral i/o
psd5xx family 6-56 page register the page register is 4 bits wide and consists of four d flip flops.the outputs of the register (pgr0 ?pgr3) are connected to the input bus of the zpld. by including the four outputs as inputs to the dpld, the addressing capability of the microcontroller is increased by a factor of 16. figure 29 shows the page register block diagram. inputs to the four flip flops are connected to data bus d0-d3. the output of the register can be read by the microcontroller. the register can operate as an independent register to the microcontroller if page mode is not implemented. the psd5xx has a programmable security bit which offers protection from unauthorized duplication. when the security bit is set, the contents of the eprom, the psd5xx non-volatile configuration bits and zpld data are prevented from being read by eprom programmers. the security bit is set through the psdsoft software and is embedded in the compiled output file. the security bit is uv erasable and a secured part can be erased and then re-programmed. security protection figure 29. page register dpld rs0 gpld ppld zpld es0 ?3 pgr0 pgr1 pgr2 pgr3 r/w d0 d0 ?d3 d1 d2 d3 q0 q1 q2 q3 page register reset
psd5xx family 6-57 the psd5xx provides many power saving options. by configuring the pmmrs (power management mode registers), the user can reduce power consumption. table 17 shows the bit configuration of the pmmr0 and pmmr1. the microcontroller is able to control the power consumption by changing the pmmr bits at run time. standby mode there are two standby modes in the psd5xx: o power down mode o sleep mode power down in this mode, the internal devices are shut down except for the i/o ports. there are three ways the psd5xx can enter into the power down mode: by controlling the csi input, by activating the automatic power down (apd) logic, or when none of the inputs are changing and the turbo bit is off. o the csi the csi input pin is an active low signal. when low, the signal selects and enables the psd5xx. the psd5xx enters into power down mode immediately when the signal turns high. this signal can be controlled by the microcontroller, external logic or it can be grounded. the csi turns off the internal bus buffers in standby mode. the address and control signals from the microcontroller are blocked from entering the zpld as inputs. o the apd logic the apd unit enables the user to enter a power down mode independent of controlling the csi input. this feature eliminates the need for external logic (decoders and latches) to power down the psd. the apd unit concept is based on tracking the activity on the ale pin. if the apd unit is enabled and ale is not active, the 4-bit apd counter starts counting and will overflow after 15 clocks, generating a pd (power down) signal powering down the psd. if sleep mode is enabled, then pd signal will also activate the sleep mode. immediately after ale starts pulsing the psd will get out of the power down or sleep mode. the operation of apd is controlled by the pmmr (see figure 30a). pmmr1 bit 0 selects the source of the apd counter clock. after reset the apd counter clock is connected to pe7 (apd_clk) on the psd. in order to guarantee that the apd will not overflow there should be less than 15 apd clocks between two ale pulses. if clkin frequency is adequate, then it can be connected to the apd and pe7 is used for other functions. the next step is to select the ale power down polarity. usually, mcus entering power down will freeze their ale at logic high or low. by programming bit 1 of pmmr0 the power down polarity can be defined for the apd. if the apd detects that the ale is in the power down polarity for 15 apd counter clocks then the psd will enter a power down mode. to enable the apd operation, bit 2 in the pmmr0 should be set high. sleep mode the sleep mode is activated if the sleep en bit, the apd en bit, and the ale polarity bit in the pmmr are set, and the apd counter has overflowed after 15 clocks (see figure 30). in sleep mode the psd5xx consumes less power than the power down mode, with typical i cc reduced to 10 a. in this mode, the counter/timers, the interrupt controller and the zpld still monitor their inputs and respond to them. as soon as the ale starts pulsing, the psd5xx exits the sleep mode. the psd access time from sleep mode is specified by t lvdv1 . the zpld response time to an input transition is specified by t lvdv2 . power management unit
psd5xx family 6-58 clr clk apd counter apd clk pmmr1 - bit 0 to other circuits mux apd clear logic apd enable pmmr0 - bit 2 ale polarity pmmr0 - bit 1 ale reset apd clk clkin csi sleep enable pmmr1 - bit 1 sleep mode eprom select sram select i/o select power down pd z p l d figure 30. power management unit figure 30a. automatic power down unit (apd) flow chart apd disabled need apd clk yes yes no no reset set apd clk in pmmr1 bit 0 set ale pd polarity in pmmro bit 1 csi = "1" need sleep mode set sleep mode in pmmr1 bit 1 ale idle and 15 apd clock ale idle and 15 apd clock ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 ?set enable apd in pmmr0 bit 2 ?set pmmr0 bit 0 disable clocks zpld aclk, zpld rclk, tmr zpld disable clocks zpld aclk, zpld rclk, tmr zpld psd in power down mode psd in sleep mode power management unit (cont.)
psd5xx family 6-59 apd en bit ale power ale status apd counter down polarity 0 x x not counting 1 x pulsing not counting 11 1 counting (activates standby mode after 15 clocks) 10 0 counting (activates standby mode after 15 clocks) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tmr clk zpld zpld zpld apd ale pd * rclk aclk turbo cmiser enable polarity 1 = off 1 = off 1 = off 1 = off 1 = on 1 = on 1 = high pmmr0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ****** sleep apd clk mode 1 = on 1 = clkin pmmr1 table 17. power management mode registers (pmmr0, pmmr1) table 18. apd counter operation power management unit (cont.) bit 0 * = should be set to high (1) to operate the apd. bit 1 0 = ale power down (pd) polarity low. 1 = ale power down (pd) polarity high. bit 2 0 = automatic power down (apd) disable. 1 = automatic power down (apd) enable. bit 3 0 = eprom/sram cmiser is off. 1 = eprom/sram cmiser is on. bit 4 0 = zpld turbo is on. zpld is always on. 1 = zpld turbo is off. zpld will power down when inputs are not changing. bit 5 0 = zpld clock input into the array from the clkin pin input is connected. every clock change will power up the zpld when turbo bit is off. 1 = zpld clock input into the array from the clkin pin input is disconnected. bit 6 0 = zpld clock input into the the macrocell registers from the clkin pin input is connected. 1 = zpld clock input into the the macrocell registers from the clkin pin input is disconnected. bit 7 0 = in the psd5xx clock input is connected to the timer. 1 = in the psd5xx clock input is disconnected from the timer. bit 0 0 = automatic power down unit clock is connected to port e7 (pe7) alternate function input. 1 = automatic power down unit clock is connected to the psd clock input (clkin). bit 1 0 = sleep mode disabled. 1 = sleep mode enabled. bit 27 0 = reserved for future use, should be set to zero.
psd5xx family 6-60 power management unit (cont.) other power saving options the psd5xx provides additional power saving options. these options, except the sram standby mode, can be enabled/disabled by setting up the corresponding bit in the pmmr. o eprom the eprom power consumption in the psd is controlled by bit 3 in the pmmr0 ?eprom cmiser. upon reset the cmiser bit is off. this will cause the eprom to be on at all times as long as csi is enabled (low). the reason this mode is provided is to reduce the access time of the eprom by 10 ns relative to the low power condition when cmiser is on. if csi is disabled (high) the eprom will be deselected and will enter standby mode (off) overriding the state of the cmiser. if cmiser is set (on) then the eprom will enter the standby mode when not selected. this condition can take place when csi is high or when csi is low and the eprom is not accessed. for example, if the mcu is accessing the sram, the eprom will be deselected and will be in low power mode. an additional advantage of the cmiser is achieved when the psd is configured in the by 8 mode (8 bit data bus). in this case an additional power savings is achieved in the eprom (and also in the sram) by turning off 1/2 of the array even when the eprom is accessed (the array is divided internally into odd and even arrays). the power consumption for the different eprom modes is given in the dc characteristics table under i cc (dc) eprom adder. o sram standby mode the sram has a dedicated supply voltage v stby that can be used to connect a battery. when v cc becomes lower than v stby 0.6 then the psd will automatically connect the v stby as a power source to the sram. the sram standby current (i stby ) is typically 0.5 a. sram data retention voltage v df is 2 v minimum. o zero power zpld zpld power/speed is controlled by the zpld_turbo bit (bit 4) in the pmmr0. after reset the zpld is in turbo mode and runs at full power and speed. by setting the bit to ?? the turbo mode is disabled and the zpld is consuming zero power current if the inputs are not switching for an extended time of 100 ns. the propagation delay time will be increased by 10ns after the turbo bitis set to ??(turned off) if the inputs change at a frequency of less than 15 mhz.
psd5xx family 6-61 power management unit (cont.) port configuration pin status i/o port unchanged zpld output depend on inputs to the zpld address out undefined data port tri-stated special function out depending on status of clock input peripheral i/o tri-stated table 20. i/o pin status during power down and sleep mode o input clock the psd5xx provides the option to turn off the clock inputs to save ac power consumption. the clock input (clkin) is used as a source for driving the following modules: o zpld array clock input o zpld macrocell clock flip flop o apd counter clock o counter/timers clock during power down or if any of the modules are not being used the clock to these modules should be disabled. to reduce ac power consumption, it is especially important to disable the clock input to the zplds array if it is not used as part of a logic equation. the zpld array clock can be disabled by setting pmmr0 bit 5 (zpld aclk). the zpld macrocell clock input can be disabled by setting pmmr0 bit 6 (zpld rclk). the timer clock can be disabled by setting pmmr0 bit 7 (tmr clk). the apd counter clock will be disabled automatically if power down or sleep mode is entered through the apd unit. the input buffer of the clkin input will be disabled if bits 5 ?7 pmmr0 are set and the apd has overflowed. the counter/timers can operate in sleep mode if the tmr clk bit is low, but the power consumption will be based on the frequency of operation (clkin frequency). pld pld access access typical propagation recovery time recovery standby delay time to time to current normal normal consumed operation access power normal t pd 0 no access t lvdv 40 a down (note 1) (note 4) sleep t lvdv2 t lvdv3 no access t lvdv1 5 a (note 2) (note 3) (note 5) table 19. summary of psd5xx timing and standby current during power down and sleep modes notes: 1. power down does not affect the operation of the zpld. the zpld operation in this mode is based only on the zpld_turbo bit. 2. in sleep mode any input to the zpld will have a propagation delay of t lvdv2 . 3. pld recovery time to normal operation after exiting sleep mode. an input to the zpld during the transition will have a propagation delay time of t lvdv3 . 4. typical current consumption assuming all clocks are disabled and zpld is in non-turbo mode. 5. typical current consumption assuming all clocks are disabled.
psd5xx family 6-62 psd5xx counter/timer general description the psd5xx contains a powerful set of four 16 bit counter/timers, each controlled by either ppld outputs, external pins or software. the counter/timers aid the user in counting external events and/or generating accurate delays. these can be operated as counters or timers. in event-count, time capture and watchdog modes, the counter/timers work as counters, whereas in waveform and pulse modes they work as timers. all counter/timers are capable of generating interrupts through the on-board interrupt controller. each of the counter/timers consist of a counter/timer command register, counter/timer image register and counter/timer register. all four counter/timers share a global command register, a software load/store register, a freeze command register and the status register. counter/timer 2 can support watchdog operations. all counter/timers share a common clock input and delay cycle register used in scaling down the input clock to the counter/timer. the maximum resolution of the counter/timer is the input clock of the psd5xx divided by four. the maximum input clock frequency to the psd5xx is 30 mhz. figures 31 and 32 describe the general features of the counter/timers. features o four 16 bit counter/timers. o five modes of operation waveform mode pulse mode event counter mode time capture mode watchdog mode * o each counter/timer can be controlled by an input pin, dedicated ppld macrocell or software. o each counter/timer has an output to the interrupt controller. o the watchdog output is routed through the pld and can be programmed to be output at any pld output pin. o programmable input and output polarity. o counter/timer can be programmed as up or down counter, except in watchdog mode. o all counters have the operating frequency range of dc to 7.0 mhz (i.e 143 ns maximum resolution at 7.0 mhz). higher resolution can be achieved by using in conjunction with the gpld macrocells. o high resolution divisor unit for counter clocking purposes. o can easily interface with any 8 or 16 bit microcontroller or microprocessor. ( * ) counter/timer-2 can operate in watchdog mode.
psd5xx family 6-63 figure 31. counter/timer block diagram global command register delay cycle register freeze command register software load / store register status register control timer / counter 0 timer / counter 1 timer / counter 2 * timer / counter 3 ctu0 ctu1 ctu2 ctu3 * can also function as watchdog timer pa0 ?pa3 or pb0 ?pb3 psd5xx data bus terminal counts to interrupt controller and port e pe3 ?pe6 ppld macrocells watchdog output to ppld timer /counter outputs pin control psd5xx counter/timer (cont.)
psd5xx family 6-64 figure 32. counter/timer and interrupt controller interface with other internal blocks port e pin/ macrocell command input programmable clock prescaler global cmd reg dlcy reg freeze cmd reg s'ware load/store status reg counter / timer 0 counter / timer 1 counter/ timer 2 counter/ timer 3 ctu0 ctu1 ctu2 ctu3 timer outputs pa0 ?pa3 timer outputs pb0 ?pb3 port a port b timer0 out timer1 out timer2 out timer3 out timer [ 3 : 0 ] in mc2int [ 6 : 7 ] tc0 tc3 tc0 tc3 mc2tmr [ 3 : 0 ] pt2int [ 4 : 5 ] control bus intrf clkin zpld input bus and array timer macro- cell intr macro- cell interrupt controller address / data / control bus counter / timer unit mux ppld wdog2pld intr2pld timer clock clock in pe4 pe7 psd5xx counter/timer (cont.)
psd5xx family 6-65 counter name counting register image register counter 0 cntr0 img0 counter 1 cntr1 img1 counter 2 cntr2 img2 counter 3 cntr3 img3 there are four identical 16 bit counter/timers cntr0,cntr1,cntr2 and cntr3 and associated counter/timer image registers img0,img1,img2 and img3. refer to table 21 for counter name and register correspondence. all counter/timers share a common clock source. each counter/timer can be operated in either waveform / pulse mode or event counter/time capture mode. counter 2 can be set up as a watchdog timer in both modes. note that in event counter/time capture mode counter 2 can only be set up as a watch dog counter/timer, whereas in the waveform/pulse mode counter 2 can be configured as a pulse or waveform generator or as a watchdog timer. refer to table 24 for possible combinations of counter/timer modes and refer to figure 33 for additional details. each counter/timer can be controlled by an input pin or through a dedicated ppld macrocell output or by software. counter/timer outputs are available through port a or port b pins in alternate function mode (refer to the chapter on i/o ports). polarity of these inputs/outputs is software programmable. the following sections describe various command and data registers that need to be initialized for proper function of these counter/timers. counter/timer operating modes the psd5xx counter/timer has five basic modes of operation: the waveform and pulse or event counter, time capture, and watchdog. the waveform and pulse modes cannot be used in conjunction with event and time capture modes. both waveform/pulse or event count/time capture modes can set counter 2 into the fifth mode of operation, the ?atchdog?mode. the basic functional element used in all these modes is the counter/timer unit (ctu) illustrated in figure 33. this block consists of a 16 bit increment/decrement counter, and a 16 bit image register with various control signals. the key function of the image register is to enable microcontroller access of the counter without asynchronously interrupting the counter. software can configure each counter/timer using the associated command register. the counter/timer of the psd5xx employs four ctus to realize the various modes of operation. table 21. registers used by counters counter/timer operation
psd5xx family 6-66 figure 33. inside of each ctux (x = 0, 1, 2, 3) micro - controller data address software commands image reg cmd reg counter ctu x timer clock ppld macrocell or pin or software command input terminal count (tc) to interrupt controller terminal count (tc) to port e counter output at pins pa x or pb x * x = 0 to 7 * not applicable in event count or time capture modes. counter/timer operation (cont.)
psd5xx family 6-67 waveform mode in waveform mode, the counter/timer is capable of producing various pulse-width modulated (pwm) signals. the waveform mode in the psd5xx is realized using two ctus (counter/timer units) in the following combinations: ctu0 & ctu1 or ctu2 & ctu3. the outputs of ctu0 and ctu2 are available at port a and port b. refer to tables 25 and 26 for further details and configuration of these ports. ctu1 and ctu3 are internally connected to ctu0 and ctu2. the waveform mode is illustrated in figure 34 which shows a typical pwm waveform and the time slots in which two ctus are active. the waveform period is the sum of the counts for ctu0 and ctu1 (see equation 1), while the duty cycle is given by equation 2. the duty cycle of a waveform can be changed by loading a new value into the corresponding image register, and as soon as a terminal count is generated this new value gets loaded into the ctu. note that the end of a ctu time slot is indicated with terminal count signal of the active ctu. the terminal count signals are used to signal the transfer of active status between ctus. the terminal count is true whenever the counter underflows while decrementing or when the counter overflows while incrementing. period of the waveform generated = count high + count low..(1) duty cycle of the waveform generated = count high count high + count low......(2) the timing of various pulses that create a waveform signal in the above example is defined by the microcontroller via image register updates of the ctu0 and ctu1. the contents of an image register are loaded or copied to the associated counter under any of the following conditions: o terminal count of ctu1 and/or ctu3 pulses to transfer active status to ctu0 and/or ctu2. o an input pin (port e) pulses (if enabled by software). o a ppld macrocell output pulses (if enabled by software). o a command register bit is written to by the microcontroller, i.e., a software load/store (load). a waveform output is first initialized and then later modified by setting its two corresponding software load/store bits after loading of the image registers. if the counter/timer register is directly loaded by the mcu, it gets overwritten by the associated image register contents as soon as the counter/timer is active. the configuration of the ctu in the waveform mode is schematically illustrated in figure 35. the output polarity during the ctu0 time slot is controlled by bit 3 in the counter/timer command register. the output polarity during the ctu1 time slot is defined as the complement of the ctu0 polarity. similarly, the polarity of the input pin is controlled by bit 4 in the counter/timer command register. this description of the waveform mode of operation applies to ctu2 and ctu3 also. in order to change the image register values, use the freeze/freeze acknowledge protocol as described in the freeze command register section. counter/timer operation (cont.)
psd5xx family 6-68 figure 34. sample waveform (pwm) and ctu time slots (using counters/timers 0 and 1) output waveform * terminal count 0 terminal count 1 ctu0 active * output waveform is available at pin pa0 or pb0 depending on the psdsoft fitter pin assignment. ctu1 active ctu1 active ctu0 active ctu0 active counter/timer operation (cont.)
psd5xx family 6-69 figure 35. ctu control signals for waveform mode counter start counter (bit 1 of global command register) counter output (port a or b) (only counter 0 or 2) output polarity select (bit 3 of cmd register) software freeze (freeze command register) timer_clock * need two ctus together in waveform mode (ctu0 ?ctu1 or ctu2 ?ctu3). the terminal count of ctu0 drives ctu1 and the terminal count of ctu1 drives ctu0. the same applies to ctu2 and ctu3. software select (bit 2 of cmd register) software enable (bit 7 of cmd register) terminal count of other ctu * pin or macrocell (selected by bit 5 of cmd register) software gate bit (bit 6 of cmd register) increment/decrement select (bit 1 of cmd register) software load (software load / store register) terminal count (tc) to interrupt controller freeze acknowledge (status flags register) terminal count (tc) * to other ctu load / store enable/disable terminal count (tc) to port e counter/timer operation (cont.)
psd5xx family 6-70 pulse mode in pulse mode, the counter/timer is capable of generating a one shot pulse. the pulse width of the generated pulse is defined by the value loaded into the associated image register of the timer. if the counter/timer register is directly loaded by the mcu, it gets overwritten by the associated image register contents as soon as the counter/timer is active. each ctu is capable of pulse mode. as soon as the timer is active, i.e. decrementing or incrementing, a pulse is output until the timer underflows or overflows. the pulse waveform is illustrated in figure 36. the active level of this pulse is defined again by a command register bit. as can be seen in figure 37, the pulse is triggered by any of the following events: o transition on the input pin (port e) (if enabled by software). o ppld macrocell output pulses (if enabled by software). o command register bit is written to by a microcontroller (software load). as in the waveform mode, the polarity of the input pin is defined by a command register bit and the freeze/freeze acknowledge must be used whenever the image register is modified. the outputs of ctu0, ctu1, ctu2 and ctu3 are available at port a and port b. refer to tables 25 and 26 for further details and configuration of these ports. event counter mode in this mode, the counter/timer uses the ctu to count a number of events. an event is defined as a signal-transition on the counters input pin as defined by the input polarity configuration bit in the command registers or a low to high transition on the ppld macrocell output. in this mode, the image register of the ctu is used to store the contents of the counter at the rising edge of the load/store signal. this is opposed to the previous two modes in which the image register was used to load the counter. figure 38 shows the configuration of the ctu for the event-counter mode. notice that the enable signal is edge sensitive. its source is either: o pin driven. o ppld macrocell driven. all counter/timer registers must be assigned values during initialization in the event counter mode. during normal operation, the ctu increments or decrements its count when an event occurs. the image register is then immediately updated with the current count. the microcontroller can read the contents of the image register by first setting the command-register freeze bit in order to disable count updates of the image register during its read operation. the microcontroller waits for a freeze acknowledge and then accesses the image register in the usual fashion. the freeze signal effectively guarantees stable image register data during microcontroller read access, even though the ctu continues to count events. during the freeze acknowledge active state, the counter continues counting. note that for an event to be counted the events must be separated by at least one timer clock period plus two clkin clock periods. counter/timer operation (cont.)
psd5xx family 6-71 figure 36. sample pulse-mode waveform output waveform terminal count pulse trigger event ctu inactive ctu inactive ctu actived by a load/store pulse counter/timer operation (cont.)
psd5xx family 6-72 figure 37. ctu control signals for pulse mode counter start counter (bit 1 of global command register) counter output (port a or b) output polarity select (bit 3 of cmd register) software freeze ( freeze command register) timer_clock software select bit (bit 2 of cmd register) enable command (bit 7 of cmd register) pin or macrocell (selected by bit 5 of cmd register) software gating bit (bit 6 of cmd register) increment/decrement select (bit 1 of cmd register) software load (software load / store register) terminal count (tc) to interrupt controller freeze acknowledge (status flags register) load / store enable/disable terminal count (tc) to port e counter/timer (cont.)
psd5xx family 6-73 figure 38. ctu control signals for event count mode counter start counter (bit 1 of global command register) timer_clock software select (bit 2 of cmd register) enable command (bit 7 of cmd register) pin or macrocell (bit 5 of cmd register) pin or macrocell (selected by bit 5 of cmd register) software gating bit (bit 6 of cmd register) software freeze (freeze command register) * software store (software load / store register) terminal count (tc) to interrupt controller freeze acknowledge (status flags register) load / store enable/disable * count updates are continuously stored in the image register, unless frozen by the software freeze command. terminal count (tc) to port e counter/timer (cont.)
psd5xx family 6-74 time capture mode in the time capture mode, the counter/timer is capable of measuring the time (by counting clock pulses) between events. figure 39 shows the ctu configuration for time capture. all the counter/timer registers must be cleared during initialization of the time capture mode. here the counter is enabled to count via software only. the ctus continuously count. a load/store pulse triggers the storing of the counters contents into the associated image register. the image register effectively contains a ?nap shot?of the counter at the time of the pulse. the ctu store input is edge-triggered by events, the events being: o pin driven. o ppld macrocell driven. o software driven. a freeze signal is used to ensure that image data is stable during microcontroller reads which is similar to the description of event counter microcontroller read accesses. two ctus in time capture mode can be used to capture the rising and the falling edges of a pulse, the difference of the measurements being the pulse width. the counter continues to count regardless of the freeze acknowledge state. note that the time span between two consecutive edges of time capture must be greater than one timer clock cycle in order to be captured. watchdog counter/ timer counter/timer-2 can be operated as a watchdog timer in both waveform/pulse and event count/time capture modes. in event count/time capture mode, counter/timer-2 can be configured only as watchdog. figure 40 shows the control signals of the ctu when in watchdog mode. when the watchdog mode is active, ctu2 counts down and at the terminal count of counter-2 a watchdog condition occurs. to avoid the watchdog from occurring, a "write" to the software load/store bit-2 in the "software load/store register" has to take place before the counter-2 underflows. this action reloads the counter-2 with the initial count value in the image register-2. note that this initial count value cannot be changed after the watchdog mode is enabled. the terminal count signal of a watchdog could result in a pulse width that is equal to the count value loaded into the image register of counter/timer-2. the active high watchdog pulse from counter 2 is routed through the ppld, enabling the user to inverse its polarity or implement any other logic before driving the watchdog output on a user defined i/o pin. this signal could be used to drive a reset pin or trigger a non-maskable interrupt on a processor. once counter/timer-2 is set to the watchdog mode, it cannot be reconfigured by software and it can get out of the watchdog mode only by a reset. when the watchdog is enabled in power down and sleep modes, it remains active regardless of the state of bit 7 (tmr clk) in power management mode register pmmr0. the watchdog mode is enabled by setting the watchdog bit in the global command register. setting up the command register for ctu2 is not required except when ctu3 is configured in pulse mode. in this case, bit 0 of the command register for ctu2 is set to ?? counter/timer operation (cont.)
psd5xx family 6-75 counter/timer operation (cont.) figure 39. ctu control signals for time capture mode counter start counter (bit 1 of global command register) timer_clock software select (bit 2 of cmd register) pin or macrocell (selected by bit 5 of cmd register) software gate bit (bit 6 of cmd register) software freeze (freeze command register) software store (software load /store register) terminal count (tc) to interrupt controller freeze acknowledge (status flags register) store enable/disable terminal count (tc) to port e
psd5xx family 6-76 figure 40. ctu control signals for watchdog mode set watchdog bit (bit 3 of global command register) c o u n t e r 2 i m a g e 2 gpld software load (bit 2 of software load / store register) output pin wdog2pld counter output (active high) watchdog gpld output terminal count to interrupt controller terminal count to port e timer_clock en / dis load (self latching bit) counter/timer operation (cont.)
psd5xx family 6-77 counter/timer operation (cont.) counter/timer clock input all counter/timers 0 through 3 have a common clock source. the counter/timers are clocked from the output of a highly flexible and high resolution divisor unit. the divisors input is the external clock input pin. the divisor div is a number in the range of 4 < = div < = 280. refer to table 22 for exact values of div for different clock values. figure 42 details the psd5xx counter clock generation. the counter/timer clock input = (external clock input) (div) where div = n * k and n = (4 + dlcy). the value of k depends on the scale-bit (bit 0 in the global command register) in the ?lobal command register?, k = 8 when scale-bit is set to 1 and k = 1 when scale-bit is set to 0. dlcy is the number of delay cycles in the range of 0 < = dlcy < = 31 set up in the delay cycle register. the fastest clock to service the counter/timer is = (clock input / 4). the maximum external clock input value is 28 mhz and the fastest internal count frequency is 7.0 mhz, i.e., a resolution of 143 ns. (higher resolution can be achieved by using in conjunction with gpld macrocells). the default value of div is 4 (following a reset both k and dlcy contain zeroes). terminal counts (tcs) the terminal counts (tc0 ?tc3) generated by the counter/timers are made available at port e as outputs or as feedbacks to the zpld. refer to table 27a for pin assignments. the terminal counts can be used to concatenate the 16-bit counter/timers into a larger counter. only the trailing edge of the tc signal can be used as input to another counter/timer. for example, concatenating ctu0 and ctu1 requires the following ppld equation in the psdabel file: mc2t mr1 = !tc0; in order for a tc signal to come out, its respective bit in the port e special function out register must be set to 1. tc signals on port e pins can be used as inputs to the zpld. a tc signal goes high for the duration of at least four clkin periods whenever its corresponding timer counting-register overflows or underflows. figure 41 gives the timing relationship between clkin and the tc signal. figure 41. timing relationship between clkin and the tc signal. 4 clkin periods clkin tc - signal 30ns 30ns notes: 1. overflow occurs when a counter value changes from ffffh to 0000h during incrementing. 2. underflow occurs when a counter value changes from 0000h to ffffh during decrementing.
psd5xx family 6-78 dlcy scale bit div 00 4 10 5 20 6 30 7 40 8 50 9 6010 7011 8012 9013 10 0 14 11 0 15 12 0 16 13 0 17 14 0 18 15 0 19 16 0 20 17 0 21 18 0 22 19 0 23 20 0 24 21 0 25 22 0 26 23 0 27 24 0 28 25 0 29 26 0 30 27 0 31 28 0 32 29 0 33 30 0 34 31 0 35 dlcy scale bit div 1140 2148 3156 4164 5172 6180 7188 8196 9 1 104 10 1 112 11 1 120 12 1 128 13 1 136 14 1 144 15 1 152 16 1 160 17 1 168 18 1 176 19 1 184 20 1 192 21 1 200 22 1 208 23 1 216 24 1 224 25 1 232 26 1 240 27 1 248 28 1 256 29 1 264 30 1 272 31 1 280 table 22. dlcy, scale bit and div to generate different clock divisions sample calculation of timer input clock external input clock to the psd5xx is 8 mhz. if required counter/timers 0 ?3 count frequency is 1 mhz then the counter/timer clock input = (external clock input) (div) 8 mhz 1 mhz = = > (div) = 8 (div) therefore from table 22 when (div) = 8, the scale-bit in the ?lobal command register?is set to a 0 and the dlcy register to a value of 4. counter/timer operation (cont.) counter/timer clock input (cont.)
psd5xx family 6-79 counter/timer operation (cont.) figure 42. counter clock generation resulting divisor value 4 < = div < = 280 scale bit in global cmd register delay cycle register 0 < = dlcy < = 31 timer clock to counters / timers 0 ?3 clkin pin
psd5xx family 6-80 address register name address register name offset offset +a9h status flags +a8h global command +a6h dlcy +a5h software load/store +a4h freeze command +a3h cmd3 +a2h cmd2 +a1h cmd1 +a0h cmd0 +9fh cntr3 +9eh cntr3 +9dh cntr2 +9ch cntr2 +9bh cntr1 +9ah cntr1 +99h cntr0 +98h cntr0 +97h img3 +96h img3 +95h img2 +94h img2 +93h img1 +92h img1 +91h img0 +90h img0 table 23. offset address map of counter/timer-unit registers counter/timer registers registers cntr0,cntr1,cntr2 and cntr3 serve as actual counting logic. registers img0,img1,img2 and img3 serve as images of these counter/timers. depending upon the selected mode of operation, a counter can load a new value or transfer its content to the image register. registers img0 - img3 and cntr0 - cntr3 are accessible to the microcontroller only before setting the start bit (bit 1 in the global command register). when cntr0-cntr3 are active, the value in the read operation is not guaranteed to be stable and during a write operation there could be contention between the image register write and microcontroller write. therefore the access of registers cntr0-cntr3 should be suspended when the counter/timers are active. only img0, img1, img2 and img3 registers are accessible when the counter/timers are active. tables 23 and 23a give the address map for the various port and counter/timer-unit registers. this address offset map is of the host processor, relative to csiop (chip select input output port) i.e. address space allocated by the host microcontroller to access all the psd5xx embedded peripherals. table 23a is for 16-bit motorola microcontrollers which require different address offsets.
psd5xx family 6-81 address register name address register name offset offset +a8h status flags +a9h global command +a7h dlcy +a4h software load/store +a5h freeze command +a2h cmd3 +a3h cmd2 +a0h cmd1 +a1h cmd0 +9eh cntr3 +9fh cntr3 +9ch cntr2 +9dh cntr2 +9ah cntr1 +9bh cntr1 +98h cntr0 +99h cntr0 +96h img3 +97h img3 +94h img2 +95h img2 +92h img1 +93h img1 +90h img0 +91h img0 table 23a. offset address map of counter/timer-unit registers (for 16-bit motorola mcus in 16-bit mode. if 8-bit mode is selected, use table 23.) registers img0 through img3 are written to by the microcontroller to load the counter/timers with required values in waveform, pulse and watchdog mode only. to retrieve the count or time in event count or time capture modes, counter/timers store their values into img0 through img3. any access to the image registers must conform to the freeze/freeze acknowledge protocol, described later in the freeze command paragraph. counter/timer registers (cont.)
psd5xx family 6-82 global command register this is used to specify the operation mode of the counter/timer and to start or stop the counter/timer. therefore during the initialization of the counter/timer registers, the global command register should always be configured last. counter/timer registers (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** watch global counter scale dog mode start note: * = not used. at reset all bits come up as 0s. watch dog bit: when this bit is 0: watch dog mode is not selected. 1: watch dog counter/timer (counter 2) is active. this bit can be turned off by reset only. note: whenever this bit is set to 1, the counter start bit should also be set to 1. otherwise the counter/timer will always be off, i.e., once this bit is set, access to counter 2 registers and the global command registers are blocked. global mode bit: when this bit is set to a 0: all timers/counters are set to waveform or pulse mode. 1: all timers/counters are set to operate in event counter or time capture mode. note: further selection of modes is done in individual cmd registers. counter start bit: when this bit is set to 0: all ctus are disabled and can be re-initialized. 1: all ctus are enabled. scale bit: when this bit is set to 0: the clock to all counter/timers is divided by 1. 1: the clock to all counter/timers is divided by 8.
psd5xx family 6-83 command registers for counter/timers cmd0, cmd1, cmd2, cmd3: each of the counter/timer units (ctu) has one command register associated with it. a description of these various ctu command bits is provided below. refer to csiop tables 23 and 24 for their addresses and selection details. figure 43 describes the command register bits. the following is the description of counter/timer0 cmd0 register bits. bits in cmd1, cmd2 and cmd3 have similar descriptions. refer to figure 43 also. counter/timer registers (cont.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 enable/ software pin / input output select increment / mode disable gating ppld polarity polarity counter decrement select using bit for macrocell pin, load / ppld store cmd macrocell using pin or or ppld software macrocell notes: 1. at reset these bits come up as 0s. 2. in watchdog mode, cmd2 register bits are don? cares. mode select bit (0): this bit selects the counter/timer0 operation mode. after reset counter/timer0 initializes in waveform/event count mode. when this bit is set to 1: the counter/timer0 operates in pulse/time capture modes. 0: the counter/timer0 operates in waveform/event count modes. note: see table 24 for details of timer mode set up. increment/decrement bit (1): this bit is used to set the counter/timer in increment or decrement mode. the reset state is decrement mode. when this bit is set to 1: the counter/timer0 is in increment mode. 0: the counter/timer0 is in decrement mode. note: in watchdog mode counter #2 is in decrement mode only. select counter bit (2): this bit is used to select or deselect counter/timer0. at reset this bit initializes as 0 which means counter/timer0 is deselected. when this bit is set to 1: counter/timer0 is selected (counting enabled). 0: counter/timer0 is deselected (counting disabled). after a counter/timer is started by the global command register, it can be re-configured by changing the individual command register. the steps to re-configure a counter/timer are: 1. disable the counter/timer by writing a ??to the select counter bit (bit 2) of the command register. 2. change the counter/timer configuration by writing the new value (bit 2 remains at ?? to the command register. 3. enable the counter/timer again by writing the new value with bit 2 set to ??to the command register.
psd5xx family 6-84 command registers for counter/timers cmd0, cmd1, cmd2, cmd3 (cont.) output polarity bit (3): this bit is valid only in waveform or pulse mode and is used to select the polarity of the active output signal of the counter/timer0. at reset this bit initializes as 0 which means the active output state is low. when this bit is set to a 1: the active output state is high. 0: the active output state is low. input polarity bit (4): the state of this bit determines the polarity of the active input control signal to the counter/timer0 and is valid only for input pin. at reset this bit initializes as 0 which means that the input active is high. when this bit is set to a 1: the input active is low. 0: the input active is high. pin / ppld macrocell bit (5): this bit determines whether the counter/timer0 gets its input command for load/store and enable/disable from the psd5xx pin or from the ppld macrocell output. at reset this bit initializes as 0 which means that the input command is coming from the psd5xx ppld macrocell. when this bit is set to a 1: the counter/timer0 input command is coming from the pin. 0: the counter/timer0 input command is coming from the ppld macrocell output. software gating bit for this bit gates the load/store command activated by the load/store commands (6): psd5xx pin or ppld macrocell. at reset this bit initializes as 0 which means that the load/store command activated by the pin or macrocell is permitted through. when this bit is set to 1: load/store operation activated by pin or macrocell is not permitted through. 0: load/store operation activated by pin or macrocell is permitted through. to further decide between the pin and ppld macrocell, use bit 5 (pin/ppld macrocell). enable/disable using pin, this bit determines whether the enable/disable ppld macrocell or software command is activated by the psd5xx pin, ppld macrocell bit (7): or by software. at reset this bit initializes as 0, which means that the enable/disable command is activated by the pin or ppld macrocell. when this bit is set to 1: enable/disable command by pin or macrocell is overridden by software (only bit 2 of this register will enable or disable the counter). 0: enable/disable command is activated by pin or macrocell output. to further decide between the pin and ppld macrocell use bit 5 (pin / ppld macrocell bit). counter/timer registers (cont.)
psd5xx family 6-85 from counter ppld macrocell output mc2tmr [ 3 : 0 ] counter control input pin timer [ 3 : 0 ] in input polarity bit 4 of cmd0 register software select counter bit 2 of cmd0 register software load/store bit0 of software load /store register freeze command bit0 of freeze command register pin or macrocell select bit 5 of cmd0 register software gating bit for load / store commands from pin or macrocell bit 6 of cmd0 register enable / disable using pin, macrocell or software bit 7 of cmd0 register mux enable / disable signal to timer level sensitive load / store signal to timer rising edge sensitive figure 43. enable/disable and load/store generation counter/timer registers (cont.)
psd5xx family 6-86 configuring the mode of operation of the counter/timers: using the global mode bit of the global command register and mode select bit of the command register of counter/timers 0 3, individual counter/timer modes of operation can be set up. refer to table 24. notice that all the counter/timers can either operate in waveform/pulse or event count/time capture modes, but not in all four modes at the same time. counter/timer registers (cont.) mode select bit global mode bit (command modes modes (global command registers of of of register) counter/timers counter/timers counter/timer2 0 ?3 cmd0, cmd1, 0, 1 and 3 cmd2 and cmd3) 0 0 waveform waveform or watchdog 0 1 pulse pulse or watchdog 1 0 event counter watchdog only 1 1 time capture watchdog only freeze command register when a microcontroller needs to access the contents of the image registers (img0-img3) it does so by first setting the command register freeze bit in order to disable the timer state-machine accesses of the image register. the microcontroller waits for the freeze acknowledge bit in the counter/timer status register to be set to 1 and then it accesses the image register as an address location. the freeze acknowledge signal effectively guar- antees stable image register data during microcontroller read/write cycles even though the counter/timer continues to count. the freeze acknowledge bit gets cleared after the negation of freeze. the freeze command bits are set and cleared by the microcontroller software. the freeze command register and the software load/store register should not be set at the same time. it is recommended that the registers be accessed individually. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** freeze freeze freeze freeze ctu3 ctu2 ctu1 ctu0 note: * = not used. table 24. counter/timer modes
psd5xx family 6-87 software load/store register: each bit in this register enables a load to the corresponding counter/timer from its associated image register in waveform, pulse or watchdog modes. the actual counts are stored in their corresponding image register in event counter or time capture modes. bit 6 of the command register must be set to ??before writing to the software load/store register. counter/timer registers (cont.) software load/store 0 bit: if this bit is set to 1: counter/timer0 cntr0 gets loaded from the image register img0 or cntr0 stores into img0 based on the mode of operation ** . software load/store 1 bit: if this bit is set to 1: counter/timer1 cntr1 gets loaded from the image register img1 or cntr1 stores into img1 based on the mode of operation ** . software load/store 2 bit: if this bit is set to 1: counter/timer2 cntr2 gets loaded from the image register img2. software load/store 3 bit: if this bit is set to 1: counter/timer3 cntr3 gets loaded from the image register img3 or cntr3 stores into img3 based on the mode of operation ** . ** load operation takes place in waveform, pulse and watchdog mode. store operation takes place in event count and time capture mode. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 **** software software software software load/store 3 load/store 2 load/store 1 load/store 0 note: * = not used. the software load/store bits are automatically cleared by the served counter. in addition to four ctu registers, there are delay cycle and counter/timer status registers. these are summarized on the following pages.
psd5xx family 6-88 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 **** frezack3 frezack2 frezack1 frezack0 notes: at reset all these bits intialize as 0's. * = not used. status flags register there are eight read-only status flags. the lower four bits represent freeze acknowledge bits. counter/timer registers (cont.) frezack bits these freeze acknowledge bits are useful in the freeze/freeze acknowledge protocol. after the microcontroller senses that the frezack bit is being set it proceeds to access the image register for a read or write operation. frezack0 bit: when this bit is 1: image register access is granted. 0: image register access is not granted. frezack1 bit: when this bit is 1: image register access is granted. 0: image register access is not granted. frezack2 bit: when this bit is 1: image register access is granted. 0: image register access is not granted. frezack3 bit: when this bit is 1: image register access is granted. 0: image register access is not granted. dlcy register: bits < 4:0 > of the dlcy register are used to assign delay cycles to the counter/timer. various clock scaling values possible are 0 through 31 (decimal). at reset these bits initialize as 0. if necessary, the user has the option to set these bits up to generate delay cycles (dlcy) to scale down the counter/timer clock (see table 24). bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *** dlcy4 dlcy3 dlcy2 dlcy1 dlcy0 note: * = not used.
psd5xx family 6-89 load/store the load operation transacts an image register (e.g. img0) write into its counter/timer register (e.g. cntr0), whereas in the store operation the counter/timer register (e.g. cntr0) writes back into the image register (e.g. img0). these signals are valid only when a counter/timer is active. they are rising edge sensitive and are used to load a counter with a required value or to store the counter value in the associated image register. in waveform, pulse and watchdog modes the microcontroller writes into an image register. the respective counter/timer uses that value as its initial counting value. the data transfer operation from an image register into its corresponding counter is called load. in event counting and time capture modes the counter/timer counts event pulses or timer clock cycles, respectively. an external event or a software command can cause a data transfer from the counting element into its image register. this operation is defined as store. these operations are triggered by: o software command o terminal count (in waveform mode only) o ppld macrocell output o input pin refer to counter/timer command register and figure 43 for specific details. enable/disable these signals are used to enable or disable the counting of the counter/timers. these signals are controlled by: o software command (bits 2 and 7 of the command registers). o ppld macrocell output o input pin event count mode: in event count mode the enable/disable signal is edge sensitive and is connected to the event input signal through the ppld or pin. in time capture mode the enable/disable signal can be set by a software command only. refer to counter/timer command register and figure 43 for specific details. counter/timer input/output each counter can use individual control inputs in port e as input load/store or enable/disable signals, and counter/timer outputs in port a or port b by selecting alternate and special functions on the pins assigned to them. the outputs are used in waveform and pulse modes in which the counters generate output waveforms or pulses. the inputs can be used in all modes of operation except watchdog to create the load/store and/or enable/disable control signals. port e can be configured as outputs for terminal count. terminal count is also available as zpld inputs (via pin feedback). refer to tables 25, 26 and 27 for further details and configuration of these ports. ppld macrocell the enable/disable or load/store inputs of each counter/timer can be selected through a ppld macrocell, whose inputs are two product terms ptt0 and ptt1 from the pplds and-array. the polarity of the ppld macrocell output is programmable. the output of the ppld macrocell which is the enable/disable and/or load/store input to the counter/timer can be in a combinatorial mode or register mode. figure 44 shows the details of the ppld macrocell. refer to the ?pld?section for further information on the ppld. counter/timer (cont.)
psd5xx family 6-90 figure 44. ppld macrocell for each counter/timer and array timer [ 3 : 0 ] in clkin reset wdog2pld (internal feedback) polarity select counter / timer bit 5 of command register zpld input bus pin or macrocell select input mux comb / reg select mux pr dq q c timer _clock (prescaled clk) mc2tmr * timer input pin pt t 0 pt t? * * these are four similar macrocells with outputs mc2tmr[3:0] .abl file counter/timer (cont.)
psd5xx family 6-91 counter/timer (cont.) i/o ? port a, b, e ports a, b and e have the capabilities for counter/timer alternate and special functions, e.g. counter/timer out, load/store, enable/disable, etc. refer also to the chapter on i/o ports for further details. table 25. port pin special function out pa0 timer0_out pa1 timer1_out pa2 timer2_out pa3 timer3_out port pin special function out pb0 timer0_out pb1 timer1_out (in pulse mode only) pb2 timer2_out pb3 timer3_out (in pulse mode only) special function assignment port a: timer outputs in pulse or waveform modes can be tapped out of these pins: pa0 ?pa3. in order for the following timer outputs to drive their corresponding port pins, set the respective bits in the special function register of port a to ones. table 26. port b: timer outputs in pulse or waveform modes can be tapped out of these pins: pb0 ?pb3. in order for the following timer outputs to drive their corresponding port pins, set the respective bits in the special function register of port b to ones. the decision which of port a or b pins are used as timer outputs is done by the psdsoft fitter.
psd5xx family 6-92 port pin alternate function in pe3 timer0_in pe4 timer1_in pe5 timer2_in pe6 timer3_in i/o ? port a, b, e (cont.) port e: timer[3:0] _ inputs can have different control functions such as timer load/store and/or enable/disable, based on how these pins are configured in the timer command registers. table 27. counter/timer (cont.) port pin special function out pe4 tc0 pe5 tc1 pe6 tc2 pe7 tc3 table 27a. the terminal counts (tc0 ?tc3) generated by each counter/timer are available at port e (pins pe4 ?pe7) as shown in table 27a. to connect tc0 ?tc3 to port e pins, set the corresponding bits in the special function register to ??
psd5xx family 6-93 counter/timer (cont.) sample counter/timer0 initialization in pulse mode following is a sample initialization routine for counter/timer0 to operate in pulse mode. the assembly language commands do not correspond to any particular microcontroller. configure csiop for microcontroller access to counter/timer registers and i/o ports for initialization of counter/timers. for the values of each register, refer to tables 30 and 31. use psdsoft supplied by wsi to configure the portion related to counter/timers. also refer to the section on the psd5xx i/o ports. clear all counter/ timers load cntr0, 0000h ; clear counter/timer 0 load cntr1, 0000h ; clear counter/timer 1 load cntr2, 0000h ; clear counter/timer 2 load cntr3, 0000h ; clear counter/timer 3 scaling of clock (common to all counter/timers) load dlcy, 02h ;delay cycles(dlcy) = 2, k value is selected in ;global register by setting scale-bit counter/timer 0 initialization (command register0 cmd0) load cmd0, 6fh ;pulse mode (d0 = 1) ;increment (d1 = 1) ;select counter/timer (d2 = 1) ;output pulse active high (d3 = 1) ;load signal on input pin high going transition (d4 = 0) ;input control from pin (not ppld macrocell) (d5 = 1) ;load&store control activated by pin (d6 = 0) ;enable count (d7 = 1) load img0,fff7h ;load counter/timer0 image register with count (pulse width) ;needed (pulse duration of 8 timer clock cycles) load special reg a,1 ;configure pa0 as a timer = 0 output by writing a ??to port a ;special function register global register configuration load global, 03h ;non watchdog mode ;pulse mode ;all ctus enabled ;scale-bit = 1 ;input clock is divided by 6 now if pin pe3 on port e is input with a high going signal: o this signal causes counter/timer0 to get a value (fff7h) loaded from its associated image register (img0) and causes the counter/timer0 to start counting from fff7h (increment) until it overflows and issues a terminal count0 (tc0). o during counting port a pin (pa0) outputs a high going one-shot pulse with a width equal to (max count possible ? initial count value loaded, i.e. 8 timer clock cycles in this example). o if the interrupt controller is configured to receive tc0, it will cause the interrupt int0 to occur.
psd5xx family 6-94 general description the psd5xx includes logic for sensing, masking, priority decoding and identifying up to eight internal interrupts. the psd5xx interrupt controller can generate interrupts from two dedicated ppld product terms, two ppld macrocell outputs and four terminal-count outputs of the counter/timer unit. the four interrupts generated by the ppld can be user defined using the wsi psdsoft windows compatible pc based software. figure 45 details the basic building blocks of the psd5xx interrupt controller and figure 46 shows its interface with other sections of the psd5xx. interrupt controller features the psd5xx interrupt controller has the following features: o can accept eight interrupt inputs o ppld product terms, ppld macrocell outputs and terminal counts (tcs) of counter/timers can cause interrupts. o interrupts generated from the ppld canbe user defined. o all interrupt inputs are priority decoded, ir7 has highest priority and ir0 the lowest priority. o each interrupt can be configured as either edge or level sensitive using the edge/level register. o each interrupt can be individually masked using a mask register. o at reset all interrupts are masked. o interrupt request latch provides the status of all interrupts. o reading an interrupt vector location clears the corresponding pending interrupt. o any of these interrupts trigger a global interrupt output available as an output at port e (pe2) and/or as an input to the ppld. interrupt operation on reset all registers and latches are cleared and all interrupts are masked. during initialization of the interrupt controller, relevant interrupts are un-masked and defined whether edge or level sensitive. when one or more interrupts are raised high, the ?nterrupt request latch?latches in all the non-masked interrupts. a 3-bit priority encoder assigns the priority to the non-masked pending interrupts. the mcu (microcontroller) can clear the edge-sensitive pending interrupts by reading the ?nterrupt read clear register? level-sensitive interrupts continue to be pending even after the mcu reads the ?nterrupt read clear register? the mcu would typically service each interrupt in sequence according to priority. refer to table 28 regarding priorities of various interrupts. any of these interrupts trigger a global interrupt output available as an input to the ppld (intr2pld) and as output at port e (pe2). refer to figures 45 and 46 for details of the interrupt architecture. interrupt priority ir 7 highest ir 6 ^ ir 5 ^ ir 4 ^ ir 3 ^ ir 2 ^ ir 1 ^ ir 0 lowest table 28. interrupt priority table
psd5xx family 6-95 figure 45. interrupt controller block diagram macro- cell product terms from timer terminal counts tc3 thru tc0 int 7 int 6 int 5 int4 int 3 int 2 int 1 int 0 edge/level sensitivity select register data bus mask register global interrupt output to pe2 and pld global clear read vector read request decoder decoder priority encoder interrupt controller (cont.)
psd5xx family 6-96 figure 46. interrupt controller interface with other internal blocks port e pin/ macrocell command input prescaled clock in timer [ 3 : 0 ] in mc2int [ 6 : 7 ] pt2int [ 4 : 5 ] intr2pld mc2tmr [ 3 : 0 ] control bus intrf clkin zpld input bus and array timer macro- cell intr macro- cell address / data / control bus timer /counter unit mux programmable clock prescalar ppld interrupt controller int0 ? int3 int4 int5 int6? int7 int sense register mask register read rqst register read clear register priority status reg tc0 ?c3 * timer [ 3:0 ] out intr out timer outputs pa0 ?pa3 timer outputs pb0 ?pb3 port a port b * tc: terminal count of timer interrupt controller (cont.)
psd5xx family 6-97 interrupt operation (cont.) command registers all the eight interrupts can be individually masked using a mask register. writing ?nes? into these mask bits enables the associated interrupts. reset masks all interrupts. interrupts can also be defined as either level sensitive or edge sensitive using a sensitivity bit in the interrupt edge/level sensitivity select register. tables 29 and 29a give the address map for various port and interrupt command/status registers. this address offset map is of the host processor, relative to the csiop (chip select input output port) i.e., address space allocated by the host microcontroller to access all the psd embedded peripherals. address register name address register name offset offset +d4h interrupt read clear +d3h interrupt mask +d2h interrupt edge/level select +d1h interrupt request latch +d0h interrupt priority status table 29. offset address map of interrupt registers address register name address register name offset offset +d5h interrupt read clear +d2h interrupt mask +d3h interrupt edge/level select +d0h interrupt request latch +d1h interrupt priority status table 29a. offset address map of interrupt registers (for 16-bit motorola mcus in 16-bit mode. if 8-bit mode is selected, use table 29.) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mask7 mask6 mask5 mask4 mask3 mask2 mask1 mask0 interrupt mask register bits mask 0 ... mask 7 correspond to interrupt 0 ... interrupt 7. when these bits are set to 1 = unmasked 0 = masked at reset these bits initialize as 0 and all interrupts are masked. the interrupt registers listed in tables 29 and 29a are described below. interrupt controller (cont.)
psd5xx family 6-98 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sense7 sense6 sense5 sense4 sense3 sense2 sense1 sense0 interrupt operation (cont.) interrupt edge/level select register bits sense 0 ... sense 7 correspond to interrupt 0 ... interrupt 7. when these bits are set to 1 = level sensitive 0 = edge sensitive (positive edge) at reset these bits initialize as 0 i.e., all interrupts come up as edge sensitive. interrupt read clear register this is a read only register. reading this register during initialization clears all the pending edge sensitive interrupts. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ir 7 ir 6 ir 5 ir 4 ir 3 ir 2 ir 1 ir 0 interrupt request latch register bits ir 0...ir 7 correspond to interrupt 0 ... interrupt 7. when any of these bits are set by the interrupt controller to a ?? the corresponding interrupt is pending service. the mcu can read the interrupt request latch which shows the status of all interrupts. the entire interrupt request latch can be cleared by reading the interrupt read clear register, but level sensitive interrupts cannot be cleared. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 * *** * vect 2 vect 1 vect 0 note: * = reserved for future use, bits set to zero. interrupt priority status register the value of these 3 bits (vect2, vect1 and vect0) indicates the highest priority of the interrupt to be serviced among multiple interrupts pending. refer to the table above for priorities of various interrupts. reading this register clears the highest pending interrupt. interrupt controller (cont.)
psd5xx family 6-99 interrupt controller (cont.) interrupt operation (cont.) input/output interrupt inputs int4 and int5 originate from two dedicated ppld product terms pt2int4 and pt2int5. interrupt inputs int6 and int7 originate from the outputs of the ppld macrocells mc2int6 and mc2int7 as described in the next section and the remaining interrupt inputs int0 through int3 originate from four terminal-count (tc) outputs of the counter/timers. if an external event has to cause an interrupt in the psd5xx, it has to be routed through the ppld. regarding output from the interrupt controller, whenever an unmasked interrupt occurs, a global interrupt signal is generated. the global interrupt signal can be used as a zpld input (intr2pld). refer to figure 45 for details. it can also be driven off the chip by using the special-function out capability of port e (pe2) as intr_out. in either case, the global interrupt indicates to the mcu that an internal psd5xx interrupt has occurred. refer to the section on i/o ports for specific details of setting up the port functions. ppld macrocell interrupt inputs int6 and int7 originate two dedicated ppld macrocells. each of these ppld macrocells have two product terms as inputs that are inputted into a ppld macrocell as shown in figure 47. the outputs of both ppld macrocells mc2int6 and mc2int7 are either combinatorial or register mode. the polarity of the product terms is programmable. refer to the section on ?pld?for further reference on the ppld. interrupt flowchart the flowchart in figure 48 explains the overall initialization and the servicing of the interrupts.
psd5xx family 6-100 figure 47. ppld interrupt macrocell and array pt pt pt pt pt pt clkin reset intr2pld (internal feedback) similar interrupt macrocell interrupt macrocell polarity select comb / reg select comb / reg select interrupt module pt2int4 pt2int5 zpld input bus mux dq c mc2int 7 pt = product terms mc2int6 int 7 int6 pe2 tc0 tc1 tc2 tc3 int4 int5 int2 int3 int0 int1 interrupt controller (cont.)
psd5xx family 6-101 figure 48. interrupt flowchart configure interrupt source pld and / or timer count i.e. unmask reqd intrpt interrupt occurred ? determine priority of the interrupt keep low priority interrupts pending service high priority interrupt are all interrupts serviced ? continue executing main loop until interrupt occurs interrupt initialization clear all pending bits (read clear register define edge or level sensitive no yes no yes interrupt controller (cont.)
psd5xx family 6-102 system configuration the csiop signal, which is generated by the dpld, selects the internal i/o devices or registers. the csiop signal takes up 256 bytes of address space and is defined by the user in the psdsoft software. the following is an address offset map for the various devices relative to the csiop base address. some motorola 16-bit microcontrollers have a different data bus/data byte orientation. this requires a different address offset for the internal psd5xx i/o devices or registers. tables 30a and 31a in this section are for this group of microcontrollers which include the m68hc16, m68302 and m683xx. the following table is the address map offset of the i/o port registers. address offset register name port a port b port c port d port e data in 00 01 10 11 20 control 02 03 12 13 22 data out 04 05 14 15 24 direction 06 07 16 17 26 open drain 18 19 special function 08 09 28 pld ?i/o 0a 0b 2a macrocell out 0c 0d 2c table 30. i/o register address offset address offset register name port a port b port c port d port e data in 01 00 11 10 21 control 03 02 13 12 23 data out 05 04 15 14 25 direction 07 06 17 16 27 open drain 19 18 special function 09 08 29 pld ?i/o 0b 0a 2b macrocell out 0d 0c 2d table 30a. i/o register address offset (for 16-bit motorola mcus in 16-bit mode. if 8-bit mode is selected, use table 30.)
psd5xx family 6-103 system configuration (cont.) register name address register name address offset offset page register e0 intr. read clear d4 intr. mask d3 intr. edge/level d2 intr. request d1 intr. priority d0 latch status vm c0 pmmr1 b1 pmmr0 b0 status flags a9 global command a8 dlcy a6 software load/store a5 freeze command a4 cmd3 a3 cmd2 a2 cmd1 a1 cmd0 a0 cntr3 9f cntr3 9e cntr2 9d cntr2 9c cntr1 9b cntr1 9a cntr0 99 cntr0 98 img3 97 img3 96 img2 95 img2 94 img1 93 img1 92 img0 91 img0 90 table 31. other register address offset
psd5xx family 6-104 system configuration (cont.) register name address register name address offset offset page register e1 intr. read clear d5 intr. mask d2 intr. edge/level d3 intr. request d0 intr. priority d1 latch status vm c1 pmmr1 b0 pmmr0 b1 status flags a8 global command a9 dlcy a7 software load/store a4 freeze command a5 cmd3 a2 cmd2 a3 cmd1 a0 cmd0 a1 cntr3 9e cntr3 9f cntr2 9c cntr2 9d cntr1 9a cntr1 9b cntr0 98 cntr0 99 img3 96 img3 97 img2 94 img2 95 img1 92 img1 93 img0 90 img0 91 table 31a. other register address offset (for 16-bit motorola mcus in 16-bit mode. if 8-bit mode is selected, use table 31.) register name register function data in this register is used to read the input on the port pins. control a 0 sets the corresponding port pin in address out mode. a 1 sets the pin in mcu i/o mode. data out holds the output data in the mcu i/o mode. direction this register is used to control the data flow in the i/o ports. a 0 sets the corresponding pin as an input pin. a 1 sets the pin as an output pin. open drain a 0 sets the corresponding pin driver as a cmos driver. a 1 sets the pin driver as an open drain driver. special function a 1 sets the corresponding port pin as timer or interrupt output. pld ?i/o a read only status register; a 1 indicates the corresponding pin is configured as a pld pin. macrocell out this register holds the outputs of the gpld macrocells. table 32. i/o register function
psd5xx family 6-105 system configuration (cont.) register name register function page register a 4-bit register that supports paging. intr. read reading this register clears all the pending edge sensitive clear interrupts. intr. define interrupt input as level or edge sensitive. edge/level intr. mask mask selected interrupt input. intr. a 1 in the register indicates the corresponding interrupt is request latch pending. intr. the register indicates which pending interrupt has the highest priority status priority. 1. configures the psd sram to be accessed by psen as vm program space (8031 design). 2. enable the peripheral i/o mode of port a. pmmr0 power management registers; enable the psd power down mode pmmr1 and other power saving configurations. status flags counter/timer freeze acknowledge bits. global specifies the counter/timer operation mode; and to start or stop command the counter/timers. dlcy specifies the delay cycles to the counter/timers. software this register enables a load (to the counter/timer) or store load/store (in the image register) operation. freeze this register disables the timer state-machine before access to the command image register is allowed. cmd3 ?0 command registers for the configuration of the counter/timers. cntr3 0 the four 16-bit counter/timers. img3 ?0 the image registers for cntr3 0. table 33. other register function
psd5xx family 6-106 reset input the reset input to the psd5xx (reset) is an active low signal which resets some of the internal devices and configuration registers. the timing diagram in the ac/dc characterization section shows the reset signal timing requirement. the active low range has a minimum t1 duration. after the rising edge of reset, the psd5xx remains in reset during t2 range. (see figure 59). the psd5xx must be reset at power up before it can be used. zpld and memory during reset while the reset input is active, the zpld generates outputs as defined in the psdabel equations. the eprom and sram blocks respond to the microcontroller bus cycle during reset, but the data is not guaranteed. register values during and after reset table 34 summarizes the status of the volatile register values during and after reset. the default values of the volatile registers are ??after reset. zpld macrocell initialization the d flip flops in the macrocells in the gpld can be cleared by: o a product term (.re) defined by the user, in psdabel or o the macro-rst (reset) input, enabled and defined in psdabel. the timer and interrupt controller macrocells in the ppld are always cleared by the reset input. register name device reset state control port a, b, c, d, e set to ?? (address out mode) data out (data or address) port a, b, c, d, e set to ?? direction port a, b, c, d, e set to ???input mode open drain port c, d set to ???cmos outputs page register page logic set to ? pmmr0, pmmr1 power management unit set to ? vm volatile memory set to ? dlcy timer set to ? cmd0 ?cmd3 timer set to ?? clear status flags timer set to ?? clear global command timer set to ?? clear img0 ?img3, cntr0 ?cntr3 timer undefined interrupt interrupt controller set to ?? disabled system configuration (cont.) table 34. registers reset values port configuration reset standby mode port i/o input unchanged zpld output active depend on inputs to the zpld address out tri-stated not defined data port tri-stated tri-stated special function out tri-stated depending on status of clock input to the counter/timer peripheral i/o tri-stated tri-state table 35. i/o pin status during reset and standby mode
psd5xx family 6-107 symbol parameter condition min max unit t stg storage temperature cldcc ?65 + 150 ? pldcc ?65 + 125 ? commercial 0 + 70 ? operating temperature industrial ?40 + 85 ? military ?55 + 125 ? voltage on any pin with respect to gnd ?0.6 + 7 v v pp programming supply voltage with respect to gnd ?0.6 + 14 v v cc supply voltage with respect to gnd ?0.6 + 7 v esd protection > 2000 v symbol parameter condition min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v absolute maximum ratings operating range recommended operating conditions note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. range temperature v cc v cc tolerance -70 -90 -12 -15 -20 commercial 0 c to +70? + 5 v 10% 10% 10% 10% 10% industrial 40 c to +85? + 5 v 10% 10% 10% military 55 c to +125? + 5 v 10%
psd5xx family 6-108 ac/dc parameters the following tables describe the ac/dc parameters of the psd5xx family: o dc electrical specification o ac timing specification zpld timing combinatorial delays synchronous clock mode asynchronous clock mode microcontroller timing read timing write timing peripheral mode timing power down and reset timing psd5xx specific timings counter/timer timing interrupt controller timing following are some issues concerning the parameters presented: o in the dc specification, the supply current is given for different modes of operation. before calculating the total power consumption, determine the percentage of time that the psd5xx is in each mode. also the current is considerably different if the zpld_turbo bit is "off" and eprom_cmiser is "on". o the ac power component provides the zpld, eprom, sram and timer ma/mhz specification. figure 49 shows the zpld ma/mhz as a function of the number of product terms (pt) used. o in the zpld timing parameters add the required delay when zpld_turbo is "off". o in the mcu timing specification, add the required time delay when eprom_cmiser is "on".
psd5xx family 6-109 0 20 60 80 100 120 40 01015 5 20 25 pt100% pt25% bus frequency ?(mhz) i cc ?(ma) turbo on turbo on turbo off turbo off ac/dc parameters (cont.) figure 49. zpld i cc / frequency consumption (psd5xx b1 versions) (5 v 10%)
psd5xx family 6-110 symbol parameter conditions min typ max unit v cc supply voltage all speeds 4.5 5 5.5 v v ih high level input voltage 4.5 v < v cc < 5.5 v 2 v cc +.5 v v il low level input voltage 4.5 v < v cc < 5.5 v 0.5 0.8 v v ih1 reset high level input voltage (note 1) .8 v cc v cc +.5 v v il1 reset low level input voltage (note 1) ?.5 .2 v cc ?1 v v hys reset pin hysteresis 0.3 v v ol output low voltage i ol = 20 a, v cc = 4.5 v 0.01 0.1 v i ol = 8 ma, v cc = 4.5 v 0.15 0.45 v v oh output high voltage i oh = 20 a, v cc = 4.5 v 4.4 4.49 v i oh = 2 ma, v cc = 4.5 v 2.4 3.9 v v sby sram standby voltage 2.7 v cc v i sby sram standby current v cc = 0 v 0.5 1 a i idle idle current (v stdby pin) v cc > v sby 0.1 0.1 a v df sram data retention voltage only on v stby 2v i sb standby supply power down mode csi >v cc ?3 v (note 2) 40 100 a current sleep mode csi >v cc ?3 v (note 3) 10 20 a i li input leakage current v ss < v in > v cc ? .1 1 a i lo output leakage current .45 < v in > v cc ?0 5 10 a zpld_turbo = off, 0 see f = 0 mhz (note 4) figure 49 zpld adder zpld_turbo = on, f = 0 mhz 400 700 a/pt cmiser = on 00 ma and not selected i cc (dc) operating cmiser = on and eprom (note 4a) supply current eprom adder selected (x8 data bus) 10 15 ma cmiser = on and eprom 15 20 ma selected (x16 data bus) cmiser = off 15 20 ma sram not selected 0 0 ma cmiser = on, sram sram adder selected (x8 data bus) 25 40 ma cmiser = on, sram selected (x16 data bus) 30 45 ma zpld_turbo = off zpld (note 4) i cc (ac) zpld_turbo = on 2 ma/mhz (note 4a) eprom or sram 2 ma/mhz counter/timer 1 ma/mhz dc characteristics (5 v 10% versions) notes: 1. reset input has hysteresis. v il1 is valid at or below .2v cc ?1. v ih1 is valid at or above .8v cc . 2. csi deselected or internal pd is active. 3. sleep mode bit is set and internal pd is active. 4. see zpld icc/frequency power consumption graph for details. 4.a i out = 0 ma.
psd5xx family 6-111 ac/dc parameters ? zpld timing parameters (5 v 10% versions) note: 5. ports a, c, d and latched address from adio (a0, a1, a8 ?a15). ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only. -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit i/o input or feedback to t pd combinatorial output port b, e 25 30 32 34 35 add 10 ns t rpd registered input to (note 5) 27 32 34 36 37 add 10 ns combinatorial output t ea input to output enable any input 25 28 30 32 33 add 10 ns t er input to output disable any input 25 28 30 32 33 add 10 ns t arp register clear or any input 27 30 32 34 35 add 10 ns preset delay t arpw register clear or preset any input 20 25 28 29 30 ns pulse width t ard array delay 16 18 20 22 24 ns combinatorial delays (5 v 10%)
psd5xx family 6-112 * * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameter. ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only. -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maximum frequency external feedback 1/(t s + t co ) 30.30 27.03 25.00 25.00 22.81 mhz maximum frequency f max internal feedback 1/(t s +t co ?0) 43.48 37.04 33.33 31.25 28.57 mhz (f cnt ) maximum frequency pipelined data 1/(t ch + t cl ) 50.00 41.67 35.71 35.71 33.33 mhz t s input setup time any input 15 17 19 20 21 add 10 ns t h input hold time any input 00000 0ns t ch clock high time clock input 10 12 14 15 16 0 ns t cl clock low time clock input 10 12 14 15 16 0 ns t co clock to output delay clock input 18 20 21 22 24 0 ns array delay t ard for product term any macrocell 16 18 20 22 24 0 ns expansion t min minimum clock period t ch + t cl 20 24 28 29 28 0 ns synchronous clock mode (5 v 10%) ac/dc parameters ? zpld timing parameters (5 v 10% versions)
psd5xx family 6-113 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off * unit maximum frequency external feedback 1/(t sa + t coa ) 26.32 25.00 21.74 21.74 20.41 mhz maximum frequency f maxa internal feedback 1/(t sa +t co a ?0) 35.71 33.33 27.78 27.78 25.64 mhz (f cnta ) (note 6) maximum frequency pipelined data 1/(t ch + t cl ) 41.67 41.67 35.71 35.71 33.33 mhz t sa input setup time any input 8 8 10 12 13 add 10 ns t ha input hold time any input 8 8 10 12 13 0 ns t cha clock high time any input 12 12 14 15 16 0 ns t cla clock low time any input 12 12 14 15 16 0 ns t coa clock to output any input to delay port b 30 32 36 37 38 add 10 ns t ard array delay for product term any macrocell 16 18 20 22 24 0 ns expansion t mina minimum clock period 1/f cnt 28 30 36 43 39 0 ns asynchronous clock mode (5 v 10%, note 6) note: 6. only port b has asynchronous outputs. clock into macrocell flip flop is generated by a product term. * * note: if zpld_turbo is off and the zpld is operating above 15 mhz, there is no need to add 10 ns to the timing parameter. ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only. ac/dc parameters ? zpld timing parameters (5 v 10% versions)
psd5xx family 6-114 explanation of ac symbols for non zpld timing. example: t avlx time from address valid to ale invalid. a address l logic level low or ale t r/w c power down n reset t time d input data p port signal v valid e ? q output data x no longer a valid logic level h logic level high r wr, uds, lds, ds, iord, psen z float i interrupt s chip select -70 -90** -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t lvlx ale or as pulse width 18 20 25 28 30 0 ns t avlx address setup time (note 8) 5 6 9 10 12 0 ns t lxax address hold time (note 8) 7 8 10 11 12 0 ns t avqv address valid to data valid (note 8) 70 90 120 150 200 add 10 ns t slqv cs valid to data valid 80 100 130 150 200 add 10 ns rd to data valid 8/16-bit bus (note 7) 20 32 38 40 45 0 ns t rlqv rd to data valid 8-bit bus, 8031 separate mode (note 7a) 32 38 40 45 50 0 ns rd to data valid from interrupt controller (note 7b) 32 38 40 45 50 0 ns t rhqx rd data hold time (note 7) 0 0 0 0 0 0 ns t rlrh rd pulse width (note 7) 30 32 35 38 40 0 ns t rhqz rd to data high-z (note 7) 22 25 30 33 35 0 ns t ehel e pulse width 30 32 35 38 40 0 ns t theh r/w setup time to enable 8 10 15 18 20 0 ns t eltl r/w hold time after enable 00 0 00 0 ns in 16-bit data bus 20 30 35 38 40 0 ns address input valid to mode (note 9) t avpv address output delay in 8-bit data bus 22 32 45 48 50 0 ns mode (note 9) read timing (5 v 10%) microcontroller interface ac/dc parameters (5 v 10% versions) notes: 7. rd timing has the same timing as psen, ds, lds, uds signals (in 8031 combined mode). 7a. rd and psen have the same timing for 8031 separate mode. 7b. read to data valid of the interrupt request latch and interrupt priority status. rd timing has the same timing as psen, ds, lds, uds signals. 8. any input used to select an internal psd5xx function. 9. in multiplexed mode latched address generated from adio delay to address output on any port. ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only.
psd5xx family 6-115 microcontroller interface ac/dc parameters (5 v 10% versions) note: 10. wr timing has the same timing as e, ds, lds, uds, wrl, whr signals. ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only. -70 -90** -12 -15 -20 eprom_cmiser symbol parameter conditions min max min max min max min max min max on unit t lvlx ale or as pulse width 18 20 25 28 30 ns t avlx address setup time (note 8) 5 6 9 10 12 ns t lxax address hold time (note 8) 7 8 10 11 12 ns t avwl address valid to leading edge of wr (notes 8 and 10) 18 20 25 30 35 ns t slwl cs valid to leading edge of wr (note 10) 22 25 30 35 40 ns t dvwh wr data setup time (note 10) 12 15 20 22 25 ns t whdx wr data hold time (note 10) 5 5 5 5 5 ns t wlwh wr pulse width (note 10) 18 20 25 28 30 ns t whax trailing edge of wr to address invalid (note 10) 0 0 0 0 0 ns t whpv trailing edge of wr to port output valid (note 10) 25 30 35 38 40 ns in 16-bit data bus 20 30 35 38 40 ns address input valid to mode (note 9) t avpv address output delay in 8-bit data bus 22 32 45 48 50 ns mode (note 9) write timing (5 v 10%)
psd5xx family 6-116 notes: 11. any input used to select port a data peripheral mode. 12. data is already stable on port a. 13. data stable on adio pins to data on port a. ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only. -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t avqv (pa) address valid to data valid (note 11) 45 55 60 62 65 add 10 ns t slqv (pa) cs valid to data valid 55 55 60 62 65 add 10 ns rd to data valid (notes 7, 12) 22 26 38 45 50 0 ns t rlqv (pa) rd to data valid 8031 mode 32 38 40 45 50 0 ns t dvqv (pa) data in to data out valid 22 22 25 26 28 0 ns t qxrh (pa) rd data hold time (note 7) 00000 0ns t rlrh (pa) rd pulse width (note 7) 25 30 35 38 40 0 ns t rhqz (pa) rd to data high-z (note 7) 20 25 30 33 35 0 ns port a peripheral data mode read timing (5 v 10%) -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t wlqv (pa) wr to data propagation delay (note 10) 25 27 32 35 38 0 ns t dvqv (pa) data to port a data propagation delay (note 13) 22 22 25 26 28 0 ns t whqz (pa) wr invalid to port a tri-state (note 10) 20 25 30 33 35 ns port a peripheral data mode write timing (5 v 10%) microcontroller interface ac/dc parameters (5 v 10% versions)
psd5xx family 6-117 -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t lvdv ale access time from power down 100 120 140 150 170 add 10 ns t lvdv1 ale or csi access time from sleep 120 150 170 200 200 0 ns t lvdv2 zpld propagation delay in sleep mode 600 600 600 600 600 0 ns t lvdv3 zpld recovery time after sleep mode 250 250 250 250 250 0 ns t chcl apd clock high time using pe7 10 12 14 15 16 0 ns t clch apd clock low time using pe7 10 12 14 15 16 0 ns f max apd maximum frequency using pe7 35.00 30.00 25.00 22.00 20.00 0 mhz t 1 reset active low time 150 200 250 300 300 0 ns t 2 reset high to operational device 150 200 250 300 300 0 ns power down and reset timing (5 v 10%) microcontroller interface ac/dc parameters (5 v 10% versions) ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only.
psd5xx family 6-118 notes: 14. for inputs which use ppld only. 15. this timing is only valid when read to the interrupt request latch and priority status latch are not valid. -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit f max maximum frequency 36.00 30.00 25.00 22.00 20.00 0 mhz t chcl clock high time 10 12 14 15 16 0 ns t clch clock low time 10 12 14 15 16 0 ns t chpv clock to output delay 28 30 32 33 35 0 ns t chpv1 clock to watchdog output delay 50 50 55 58 60 add 10 ns t lvch input setup time relative add 10 to rising clock edge pin input 15 17 19 20 21 (note 14) ns input setup time relative pld add 10 t lvch1 to rising clock edge combinatorial 25 27 29 31 33 (note 14) ns input t min minimum clock period 1/f max 28 33 40 45 50 0 ns counter/timer timing (5 v 10%) -70 -90** -12 -15 -20 zpld_turbo symbol parameter conditions min max min max min max min max min max off unit t iviv interrupt request input to interrupt output (note 15) 40 50 60 65 70 0 ns t rxix read vector to interrupt request clear 30 40 50 55 60 0 ns t ilil interrupt request minimum pulse width 18 20 30 35 40 0 ns t rlqv rd to data valid interrupt controller (note 7b) 32 38 40 45 50 0 ns interrupt timing (5 v 10%) ac/dc parameters ? zpld timing parameters (5 v 10% versions) ** note: revision a and previous silicon revisions are 5v 5% for 90 nsec version only.
psd5xx family 6-119 figure 50. read timing t avlx t lxax t lvlx t avqv t slqv t rlqv t rhqx trhqz t eltl t ehel t rlrh t theh t avpv address valid address valid data valid data valid address out read timing ale /as a /d (bhe) multiplexed bus address (bhe/siz0) non-multiplexed bus data non-multiplexed bus csi rd (psen, ds) (lds, uds) e r/w
psd5xx family 6-120 figure 51. write timing t avlx t lxax t lvlx t avwl t slwl t whdx t whax t eltl t ehel t wlwh t dvwh t theh t avpv address valid address valid data valid data valid address out write timing t whpv standard mcu i/o out ale/as a /d (bhe) multiplexed bus address (bhe, siz0) non-multiplexed bus data non-multiplexed bus csi wr (wrh, wrl) (lds, uds) (ds) e r/ w
psd5xx family 6-121 figure 52. peripheral i/o read timing t qxrh ( pa) t rlqv ( pa) t rlrh ( pa) t dvqv ( pa) t rhqz ( pa) t slqv ( pa) t avqv ( pa) address peripheral i/o read timing data valid ale /as a /d bus rd data on port a csi
psd5xx family 6-122 figure 54. combinatorial timing ? zpld figure 53. peripheral i/o write timing tdvqv (pa) twlql (pa) twhqz (pa) address data out a /d bus wr port a data out ale /as tpd trpd input (from port a) any output any output input (from port b, c, d, e)
psd5xx family 6-123 figure 56. asynchronous clock mode timing (product-term clock, pb macrocell only) figure 55. synchronous clock mode timing ? zpld t ch t cl t co t h t s clkin s c ooscoc o g input registered output tcha tcla tcoa tha tsa clock input registered output
psd5xx family 6-124 figure 59. reset timing t1 t2 figure 57. input to output disable/enable figure 58. asynchronous reset/preset ter tea input input to output enable/disable tarp register output tarpw reset/preset input
psd5xx family 6-125 figure 60. key to switching waveforms waveforms inputs outputs steady input may change from hi to lo may change from lo to hi don't care outputs only steady output will be changing from hi to lo will be changing lo to hi changing, state unknown center line is tri-state
psd5xx family 6-126 symbol parameter 16 conditions typical 17 max unit c in capacitance (for input pins only) v in = 0 v 4 6 pf c out capacitance (for input/output pins) v out = 0 v 8 12 pf c vpp capacitance (for wr/v pp or r/w/v pp )v pp = 0 v 18 25 pf notes: 16. these parameters are only sampled and are not 100% tested. 17. typical values are for t a = 25? and nominal supply voltages. t a = 25 ?, f = 1 mhz pin capacitance figure 61. ac testing input/output waveform figure 62. ac testing load circuit erasure and programming 3.0 v 0 v 1.5 v test point device under test 2.01 v 195 w c l = 30 pf (including scope and jig capacitance) to clear all locations of their programmed contents, expose the window packaged device to an ultra-violet light source. a dosage of 30 w second/cm 2 is required. this dosage can be obtained with exposure to a wavelength of 2537 ? and intensity of 12000 w/cm 2 for 40 to 45 minutes. the device should be about 1 inch from the source, and all filters should be removed from the uv light source prior to erasure. the psd5xx and similar devices will erase with light sources having wavelengths shorter than 4000 ?. although the erasure times will be much longer than with uv sources at 2537 ?, exposure to fluorescent light and sunlight eventually erases the device. for maximum system reliability, these sources should be avoided. if used in such an environment, the package windows should be covered by an opaque substance. upon delivery from wsi, or after each erasure, the psd5xx device has all bits in the pad and eprom in the ??or high state. the configuration bits are in the ??or low state. the code, configuration, and pad map data are loaded through the procedure of programming information for programming the device is available directly from wsi. please contact your local sales representative.
psd5xx family 6-127 68-pin 68-pin pin no. pldcc/cldcc pin no. pldcc/cldcc package package 1 gnd 35 gnd 2 adio_7 36 pe2 3 adio_6 37 pe1 4 adio_5 38 pe0 5 adio_4 39 csi 6 adio_3 40 reset 7 adio_2 41 rd 8 adio_1 42 clkin 9 adio_0 43 pb7 10 pc7 44 pb6 11 pc6 45 pb5 12 pc5 46 pb4 13 pc4 47 pb3 14 pc3 48 pb2 15 pc2 49 pb1 16 pc1 50 pb0 17 pc0 51 gnd 18 vcc 52 vcc 19 gnd 53 pd7 20 pa7 54 pd6 21 pa6 55 pd5 22 pa5 56 pd4 23 pa4 57 pd3 24 pa3 58 pd2 25 pa2 59 pd1 26 pa1 60 pd0 27 pa0 61 adio_15 28 vstby 62 adio_14 29 wr 63 adio_13 30 pe7 64 adio_12 31 pe6 65 adio_11 32 pe5 66 adio_10 33 pe4 67 adio_9 34 pe3 68 adio_8 psd5xx pin assignments
psd5xx family 6-128 80-pin 80-pin pin no. tqfp pin no. tqfp package package 1 pc7 41 pb7 2 pc6 42 pb6 3 pc5 43 pb5 4 pc4 44 pb4 5 pc3 45 pb3 6 pc2 46 pb2 7 pc1 47 pb1 8 pc0 48 pb0 9v cc 49 gnd 10 v cc 59 gnd 11 gnd 51 v cc 12 gnd 52 v cc 13 pa7 53 pd7 14 pa6 54 pd6 15 pa5 55 pd5 16 pa4 56 pd4 17 pa3 57 pd3 18 pa2 58 pd2 19 pa1 59 pd1 20 pa0 60 pd0 21 nc 61 nc 22 nc 62 adio_15 23 vstdby 63 adio_14 24 wr 64 adio_13 25 pe7 65 adio_12 26 pe6 66 adio_11 27 pe5 67 adio_10 28 pe4 68 adio_9 29 pe3 69 adio_8 30 gnd 70 gnd 31 gnd 71 gnd 32 pe2 72 adio_7 33 pe1 73 adio_6 34 pe0 74 adio_5 35 csi 75 adio_4 36 reset 76 adio_3 37 rd 77 adio_2 38 clkin 78 adio_1 39 nc 79 adio_0 40 nc 80 nc psd5xx pin assignments
psd5xx family 6-129 figure 63. drawing j5 68-pin plastic leaded chip carrier (pldcc) (package type j) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 v cc gnd pb0 pb1 pb2 pb3 pb4 pb5 pb6 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 98765432 1 68 67 66 65 64 63 62 61 adio - 0 adio -1 adio - 2 adio - 3 adio - 4 adio - 5 adio - 6 adio - 7 gnd adio - 8 adio - 9 adio -10 adio -11 adio -12 adio -13 adio -14 adio -15 pa0 vstdby wr pe7 pe6 pe5 pe4 pe3 gnd pe2 pe1 pe0 csi reset rd clkin pb7 figure 64. drawing l5 68-pin ceramic leaded chip carrier (cldcc) with window (package type l)
psd5xx family 6-130 figure 65. drawing u2 80-pin plastic thin quad flatpack (tqfp) (package type u) 60 pd0 59 pd1 58 pd2 57 pd3 56 pd4 55 pd5 54 pd6 53 pd7 52 v cc 51 v cc 50 gnd 49 gnd 48 pb0 47 pb1 46 pb2 45 pb3 44 pb4 43 pb5 42 pb6 41 pb7 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 v cc v cc gnd gnd pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 54 63 62 61 n/c adio? adio? adio? adio? adio? adio? adio? adio? gnd gnd adio? adio? adio?0 adio?1 adio?2 adio?3 adio?4 adio?5 n/c 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n/c n/c vstdby wr pe7 pe6 pe5 pe4 pe3 gnd gnd pe2 pe1 pe0 csi reset rd clkin n/c n/c (top view) psd5xx product ordering information psd5xx family devices are available in a wide range of product selections. options and combinations include: architecture speed (access time) memory size configuration mask programmability operating temperature range packages please contact your local wsi sales representative or distributor for the psdxx product selection that best fits your application and objectives. as of the print date of this databook, all psd5xx product selections are classified as ?reliminary?

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